IP Library Granted Patent US 9,183,133
Granted Patent B2
US 9,183,133 · App. 11/946,753 · Granted Nov 10, 2015

System, method, and computer program product for increasing spare space in memory to extend a lifetime of the memory

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Quick Facts
Patent No.
US 9,183,133
App. No.
11/946,753
Granted
Nov 10, 2015
Kind
B2
Abstract

A system, method, and computer program product are provided for extending a lifetime of memory. In operation, spare space in memory is increased. Additionally, a lifetime of the memory is extended, as a result of increasing the spare space in the memory.

Claims (39)

1. A method, comprising:

increasing spare space in a storage subsystem comprising a flash memory;

extending a lifetime of the storage subsystem to achieve a stored selected minimum lifetime, at least in part as a result of the increasing spare space and enabling the spare space to comprise an increased amount of the flash memory; and

delaying at least one operation that reduces the lifetime of the storage subsystem based on identifying an aspect associated with the lifetime of the storage subsystem,

wherein the increasing the spare space comprises the storage subsystem compressing data stored in the flash memory, and

wherein the increasing the spare space further comprises detecting deleted data and increasing spare space with space occupied with the deleted data.

2. The method of claim 1 , wherein the compressing is loss-less compressing.

3. The method of claim 1 , wherein the compressing is lossy compressing.

4. The method of claim 1 , wherein the flash memory comprises a plurality of blocks, and the increasing the spare space further comprises increasing a number of spare blocks of the plurality of blocks.

5. The method of claim 4 , further comprising equalizing an end of life of the plurality of blocks.

6. The method of claim 1 , further comprising increasing the spare space by removing duplicate data stored in the flash memory.

7. The method of claim 1 , wherein the flash memory includes at least one of a single-bit per cell NOR flash memory, a multi-bit per cell NOR flash memory, a single-bit per cell NAND flash memory, and a multi-bit per cell NAND flash memory.

8. The method of claim 1 , wherein the increasing the spare space further comprises compressing previously stored data in the flash memory to enable blocks occupied by the previously stored data to be incorporated into the spare space.

9. A computer program product embodied on a non-transitory computer readable medium, comprising:

computer code for increasing spare space in a storage subsystem comprising a flash memory;

computer code for extending the lifetime of a storage subsystem to achieve a stored selected minimum lifetime, at least in part as a result of the increasing spare space and enabling the spare space to comprise an increased amount of the flash memory; and

computer code for delaying at least one operation that reduces the lifetime of the storage subsystem based on identifying an aspect associated with the lifetime of the storage subsystem,

wherein the increasing the spare space comprises the storage subsystem compressing data stored in the flash memory, and

wherein the increasing the spare space further comprises detecting deleted data and increasing space with space occupied with the deleted data.

10. The computer program product of claim 9 , wherein the compressing is loss-less compressing.

11. The computer program product of claim 9 , wherein the compressing is lossy compressing.

12. The computer program product of claim 9 , wherein the flash memory comprises a plurality of blocks, and the increasing the spare space further comprises increasing a number of spare blocks of the plurality of blocks.

13. The computer program product of claim 12 , further comprising computer code for equalizing an end of life of the plurality of blocks.

14. The computer program product of claim 9 , wherein the increasing the spare space further comprises removing duplicate data stored in the flash memory.

15. The computer program product of claim 9 , wherein the flash memory includes at least one of a single-bit per cell NOR flash memory, a multi-bit per cell NOR flash memory, a single-bit per cell NAND flash memory, and a multi-bit per cell NAND flash memory.

16. An apparatus, comprising:

a storage subsystem comprising:

a flash memory;

logic for increasing spare space in the flash memory; and

logic for extending a lifetime of the storage subsystem to achieve a stored selected minimum lifetime, at least in part as a result of the increasing the spare space to comprise an increased amount of the flash memory; and

logic for delaying at least one operation that reduces the lifetime of the storage subsystem based on identifying an aspect associated with the lifetime of the storage subsystem,

wherein the spare space is increased at least in part by the storage subsystem compressing data stored in the flash memory, and

wherein the increasing the spare space further comprises detecting deleted data and increasing space with space occupied with the deleted data.

17. The apparatus of claim 16 , wherein the storage subsystem is coupled with a computer via a standard storage bus.

18. The apparatus of claim 16 , wherein the compressing is loss-less compressing.

19. The apparatus of claim 16 , wherein the compressing is lossy compressing.

20. The apparatus of claim 16 , further comprising the flash memory.

21. The apparatus of claim 20 , wherein the flash memory includes at least one of a single-bit per cell NOR flash memory, a multi-bit per cell NOR flash memory, a single-bit per cell NAND flash memory, and a multi-bit per cell NAND flash memory.

22. The apparatus of claim 16 , wherein the logic for increasing the spare space in the flash memory further operates by removing duplicate data stored in the flash memory.

Assignments (6)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034771/0272 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS INCLUDED IN SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (032856/0031) Recorded Nov 6, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034177/0257 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2012
From: SANDFORCE, INC.
To: LSI CORPORATION
Reel/Frame 028938/0413 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2007
From: DANILAK, RADOSLAV
To: SANDFORCE, INC.
Reel/Frame 020173/0767 →