Patent Assignment
Reel/Frame 034778/0480
Assignment of Assignor's Interest
Recorded: 2015-01-21
Pages: 60
Assignor
LSI CORPORATION
Executed: 2014-09-02
Assignee
SEAGATE TECHNOLOGY LLC
10200 S. DE ANZA BLVD., CUPERTINO, CALIFORNIA, 95014
Covered Properties
(25)
Variable Redundancy in a Solid State Drive
Application:
61/827,190 →
Data Decoder With Trapping Set Flip Bit Mapper
Application:
61/856,359 →
Sequential Read Optimized Variable-Sized Flash Translation Layer
Application:
61/866,672 →
Virtual Bands Concentration for Self Encrypting Drives
Application:
61/870,936 →
Translation Layer Partitioned Between a Host and a Controller
Application:
61/873,357 →
Reduced Polar Codes
Application:
61/878,163 →
Method of Erase State Handling in Flash Channel Tracking
Application:
61/879,318 →
Flash Memory Reference Voltage Detection with Tracking of Cross-Points of Cell Voltage Distributions Using Histograms
Application:
61/883,491 →
Flash Memory Read Retry Using Histograms
Application:
61/886,180 →
Variable-Size Flash Translation Layer
Application:
61/888,681 →
Generating Soft Decoding Information for Flash Memory Error Correction Using Hard Decision Patterns
Application:
61/892,328 →
Systems and Methods for Latency Based Data Recycling in a Solid State Memory System
Application:
61/892,429 →
Systems and Methods for Soft Data Utilization in a Solid State Memory System
Application:
61/893,335 →
Systems and Methods for Sub-Zero Threshold Characterization in a Memory Cell
Application:
61/896,590 →
Method to Implement Unaligned Data Bands in a Self Encrypting Solid State Drive
Application:
61/897,366 →
Reduction or Elimination of Latency Penalty Associated with Adjusting Read Thresholds for Non-Volatile Memory
Application:
61/898,947 →
Incremental Programming Pulse Optimization to Reduce Write Errors
Application:
61/902,380 →
Detection/Erasure of Random Write Errors Using Converged Hard Decisions
Application:
61/902,450 →
Systems and Methods for Soft Decision Generation in a Solid State Memory System
Application:
61/905,185 →
Eliminating or Reducing Programming Errors When Programming Flash Memory Cells
Application:
61/909,211 →
Non-Volatile Memory With Channel Tracking-Based Retry Read Voltage
Application:
61/909,447 →
Decoding with Log Likelihood Ratios Stored in a Controller
Application:
61/909,529 →
Flash Channel With Selective Decoder Likelihood Dampening
Application:
61/910,100 →
Preventing Programming Errors from Occurring When Programming Flash Memory Cells
Application:
61/918,778 →
Capacitance Coupling Parameter Estimation in Flash Memories
Application:
61/923,915 →
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Patent Security Agreement
May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Termination and Release of Security Interest in Certain Patents Included in Security Interest Previously Recorded at Reel/Frame (032856/0031)
Nov 6, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034177/0257 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 032856-0031)
Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →