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Multi Functional Camera With Multiple Reflection Beam Splitter

App. No. 14/794,548

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Golf Club Head Having Composite Tubes

App. No. 14/794,578

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Vehicle Engine Harmonic Sound Control

App. No. 14/667,164

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Voice Prompt Generation Combining Native and Remotely-Generated Speech Data

App. No. 14/322,561

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METHOD AND APPARATUS FOR REMOTELY RENDERING A FILE IN A FORMAT APPROPRIATE FOR PRINTING

App. No. 14/147,370

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REMEDY FOR MIGRAINE HEADACHE

App. No. 13/359,393

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APPARATUS AND METHOD FOR APPLYING A TIRE DRESSING FLUID TO A TIRE SURFACE

App. No. 11/188,334

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METHOD FOR SUPPORTING CASHLESS PAYMENT

App. No. 10/959,374

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TRENCH SIDE WALL CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICE

App. No. 10/430,582

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DIFFERENTIAL CIRCUIT AND PEAK HOLD CIRCUIT INCLUDING DIFFERENTIAL CIRCUIT

App. No. 10/418,197

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NONVOLATILE SEMICONDUCTOR MEMORY DEVICE PROGRAMMING SECOND DYNAMIC REFERENCE CELL ACCORDING TO THRESHOLD VALUE OF FIRST DYNAMIC REFERENCE CELL

App. No. 10/356,495

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METHOD FOR IMPROVING READ MARGIN IN A FLASH MEMORY DEVICE

App. No. 10/349,293

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SYSTEM AND METHOD FOR CHARGE RESTORATION IN A NON-VOLATILE MEMORY DEVICE

App. No. 10/338,333

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METHOD OF FORMING COPPER SULFIDE FOR MEMORY CELL

App. No. 10/314,060

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MEMORY CIRCUIT FOR SUPPRESSING BIT LINE CURRENT LEAKAGE

App. No. 10/306,080

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METHOD OF FABRICATING NITRIDATED TUNNEL OXIDE BARRIERS FOR FLASH MEMORY DEVICES HAVING STI AND LOCOS ISOLATION

App. No. 10/295,738

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METHOD OF FORMING FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER

App. No. 10/291,293

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BI-LAYER FLOATING GATE FOR IMPROVED WORK FUNCTION BETWEEN FLOATING GATE AND A HIGH-K DIELECTRIC LAYER

App. No. 10/274,063

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A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-MICRON FLASH MEMORY SEMICONDUCTOR DEVICE

App. No. 10/244,129

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PATH GATE DRIVER CIRCUIT

App. No. 10/243,433

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FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS

App. No. 10/233,906

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METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED

App. No. 10/224,737

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METHOD FOR REPAIRING OVER-ERASURE OF FAST BITS IN FLOATING GATE MEMORY DEVICES

App. No. 10/215,140

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ON-CHIP REPAIR OF DEFECTIVE ADDRESS OF CORE FLASH MEMORY CELLS

App. No. 10/200,544

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NONVOLATILE MEMORY CELL WITH A NITRIDATED OXIDE LAYER

App. No. 10/199,793

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MEMORY DEVICE AND METHOD OF MAKING

App. No. 10/189,651

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EXTRACTION OF DRAIN JUNCTION OVERLAP WITH THE GATE AND THE CHANNEL LENGTH FOR ULTRA-SMALL CMOS DEVICES WITH ULTRA-THIN GATE OXIDES

App. No. 10/178,144

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USE OF HIGH-K DIELECTRIC MATERIAL FOR ONO AND TUNNEL OXIDE TO IMPROVE FLOATING GATE FLASH MEMORY COUPLING

App. No. 10/176,594

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HARD MASK REMOVAL PROCESS INCLUDING ISOLATION DIELECTRIC REFILL

App. No. 10/165,837

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METHOD FOR INCREASING CORE GAIN IN FLASH MEMORY DEVICE USING STRAINED SILICON

App. No. 10/159,323

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METHOD AND SYSTEM FOR PROVIDING A POLYSILICON STRINGER MONITOR

App. No. 10/155,500

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METHOD OF FORMING LOW RESISTANCE COMMON SOURCE LINE FOR FLASH MEMORY DEVICES

App. No. 10/152,747

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METHOD FOR MINIMIZING NITRIDE RESIDUE ON A SILICON WAFER

App. No. 10/150,282

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SELF-ALIGNED POLYSILICON POLISH

App. No. 10/150,204

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SYSTEM FOR PROGRAMMING A FLASH MEMORY DEVICE

App. No. 10/136,033

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RELACS SHRINK METHOD APPLIED FOR SINGLE PRINT RESIST MASK FOR LDD OR BURIED BITLINE IMPLANTS USING CHEMICALLY AMPLIFIED DUV TYPE PHOTORESIST

App. No. 10/126,326

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METHODS AND SYSTEMS FOR FLASH MEMORY TUNNEL OXIDE RELIABILITY TESTING

App. No. 10/121,140

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STACKED POLYSILICON LAYER FOR BORON PENETRATION INHIBITION

App. No. 10/118,363

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METHOD OF DETERMINING LOCATION OF GATE OXIDE BREAKDOWN OF MOSFET BY MEASURING CURRENTS

App. No. 10/113,017

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MEMORY WORDLINE HARD MASK

App. No. 10/109,235

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MEMORY WITH DISPOSABLE ARC FOR WORDLINE FORMATION

App. No. 10/100,487

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USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES

App. No. 10/097,912

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OVERERASE CORRECTION METHOD

App. No. 10/099,499

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FLASH MEMORY ARRAY ARCHITECTURE HAVING STAGGERED METAL LINES

App. No. 10/096,313

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DC-DC CONVERTER, POWER SUPPLY CIRCUIT, METHOD FOR CONTROLLING DC-DC CONVERTER, AND METHOD FOR CONTROLLING POWER SUPPLY CIRCUIT

App. No. 10/087,852

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POWER-SAVING MODES FOR MEMORIES

App. No. 10/061,620

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FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME

App. No. 10/027,253

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NITRIDING PRETREATMENT OF ONO NITRIDE FOR OXIDE DEPOSITION

App. No. 10/006,529

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SEMICONDUCTOR MEMORY CAPABLE OF BEING DRIVEN AT LOW VOLTAGE AND ITS MANUFACTURE METHOD

App. No. 09/973,743

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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH VARIABLE GAIN AMPLIFIER

App. No. 09/972,152

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METHOD OF FABRICATING DOUBLE DENSED CORE GATES IN SONOS FLASH MEMORY

App. No. 09/971,483

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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS

App. No. 09/968,456

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BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE

App. No. 09/892,431

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METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A BAKING PROCESS

App. No. 09/880,366

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METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE

App. No. 09/875,056

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BURST ARCHITECTURE FOR A FLASH MEMORY

App. No. 09/829,518

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Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing

App. No. 09/824,841

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METHOD FOR FABRICATING A CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR DEVICE

App. No. 09/805,287

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PROCESSOR CAPABLE OF ENABLING/DISABLING MEMORY ACCESS

App. No. 09/791,874

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ASCENDING STAIRCASE READ TECHNIQUE FOR A MULTILEVEL CELL NAND FLASH MEMORY DEVICE

App. No. 09/794,480

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METHOD AND SYSTEM FOR DECREASING THE SPACES BETWEEN WORDLINES

App. No. 09/777,457

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PLL SEMICONDUCTOR DEVICE WITH TESTABILITY, AND METHOD AND APPARATUS FOR TESTING SAME

App. No. 09/757,492

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