IP Library Assignment 036704/0701
Patent Assignment
Reel/Frame 036704/0701

Assignment of Assignor's Interest

Recorded: 2015-10-01 Pages: 4
Assignors
GUO, TA-PEN
Executed: 2015-09-01
DIAZ, CARLOS H.
Executed: 2015-09-01
COLINGE, JEAN-PIERRE
Executed: 2015-09-01
LIN, YI-HSIUNG
Executed: 2015-09-01
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
NO. 8, LI-HSIN ROAD 6,, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, 300-77, TAIWAN
Covered Property (1)
Monolithic 3D Integration Inter-Tier Vias Insertion Scheme and Associated Layout Structure
Patent: 9,691,695 →
Application: 14/840,364 →
Publication: US 2017/0062319