Patent Assignment
Reel/Frame 037278/0757
Merger and Change of Name
Recorded: 2015-12-12
Pages: 11
Assignors
ORACLE USA, INC.
Executed: 2010-02-12
SUN MICROSYSTEMS, INC.
Executed: 2010-02-12
ORACLE AMERICA, INC.
Executed: 2010-02-12
Assignee
ORACLE AMERICA, INC.
500 ORACLE PARKWAY, REDWOOD SHORES, CALIFORNIA, 94065
Covered Properties
(100)
Method and Apparatus for Improving the Performance of Object Invocation
Patent:
6,718,550 →
Application:
08/670,684 →
Event- Driven Servers for Data Extraction and Merge for Edi Transaction Processing Using the Internet
Patent:
6,724,896 →
Application:
08/828,486 →
Reallocating Address Spaces of a Plurality of Servers Using a Load Balancing Policy and a Multicast Channel
Patent:
6,718,387 →
Application:
08/988,205 →
Method and Apparatus for High Performance Access to Data in a Message Store
Patent:
6,735,770 →
Application:
09/067,497 →
Method and Apparatus of Performing Active Update Notification
Patent:
6,721,740 →
Application:
09/092,356 →
Multiple-Thread Processor for Threaded Software Applications
Graphics System with a Variable-Resolution Sample Buffer
Patent:
6,717,578 →
Application:
09/251,840 →
Cooperative Processing of Tasks in a Multi-Threaded Computing System
Patent:
6,738,846 →
Application:
09/255,935 →
Network Proxy
Patent:
6,708,171 →
Application:
09/332,031 →
Robust Communications Connection System and Method for Shared Memory
Patent:
6,718,398 →
Application:
09/337,588 →
Method and Apparatus for Expedited File Downloads in an Applet Environment
Method and Apparatus for Constructing Dispatch Tables Which Enable Transitive Method Override
Patent:
6,725,280 →
Application:
09/374,879 →
Scheduling Storage Accesses for Rate-Guaranteed and Non-Rate-Guaranteed Requests
Patent:
6,721,789 →
Application:
09/413,043 →
System for Suspending Power to a Field Replaceable Unit Upon Receiving Fault Signal and Automatically Reapplying Power Thereto After the Replacement Unit Is Secured in Position
Patent:
6,718,472 →
Application:
09/416,001 →
Method and Apparatus for Determining Approximate Network Distances Using Reference Locations
Patent:
6,724,733 →
Application:
09/432,506 →
Method and Apparatus for Fast Packet Forwarding in Cluster Networking
Patent:
6,735,205 →
Application:
09/480,145 →
Method and Apparatus for Performing a Fast Service Lookup in Cluster Networking
Patent:
6,735,206 →
Application:
09/480,146 →
Mechanism for Merging Multiple Policies
Patent:
6,721,888 →
Application:
09/483,247 →
Method and System for Allocation of File Descriptors
Patent:
6,725,244 →
Application:
09/512,841 →
Mechanism for Reciprocal Awareness of Intent to Initiate and End Interaction Among Remote Users
Patent:
6,731,308 →
Application:
09/521,486 →
System and Method for Arranging Bits of a Data Word in Accordance with a Mask
Patent:
6,718,492 →
Application:
09/545,019 →
Disambiguating Memory References Based Upon User-Specified Programming Constraints
Patent:
6,718,542 →
Application:
09/549,806 →
Distributed Gateway System for Telephone Communications
Patent:
6,738,470 →
Application:
09/561,752 →
Method and Apparatus for Producing a 3-D Image from a 2-D Image
Patent:
6,728,422 →
Application:
09/572,718 →
Modular and Portable Deployment of a Resource Adapter in an Application Server
Patent:
6,721,777 →
Application:
09/578,528 →
Apparatus and Method for Pipelining Variable Length Decode and Inverse Quantization Operations in a Hybrid Motion-Compensated and Transform Coded Video Decoder
Patent:
6,731,686 →
Application:
09/584,834 →
Method for Resolving Dependency Conflicts Among Multiple Operative Entities Within a Computing Environment
Patent:
6,725,452 →
Application:
09/585,694 →
Graphical User Interface Layout Customizer
Patent:
6,738,079 →
Application:
09/585,978 →
Parallel Pack Instruction Method and Apparatus
Patent:
6,718,456 →
Application:
09/587,177 →
Method and Apparatus for Providing a Highly Interactive Transaction Environment in a Distributed Network
Patent:
6,728,769 →
Application:
09/588,043 →
High Availability Networking with Virtual Ip Address Failover
Patent:
6,718,383 →
Application:
09/588,130 →
High Availability Networking with Quad Trunking Failover
Patent:
6,732,186 →
Application:
09/588,144 →
Method and Device for Synchronization of Phase Mismatch in Communication Systems Employing a Common Clock Period
Patent:
6,714,612 →
Application:
09/590,935 →
Supporting Inter-Process Communication Through a Conditional Trap Instruction
Patent:
6,732,363 →
Application:
09/592,050 →
Approximate String Matcher for Delimited Strings
Patent:
6,718,325 →
Application:
09/593,907 →
Method and Apparatus for Reducing Heap Size Through Adaptive Object Representation
Patent:
6,728,852 →
Application:
09/608,312 →
Integrated Information Appliance
Patent:
6,711,419 →
Application:
09/615,366 →
Method for Filtering Instructions to Get More Precise Event Counts
Patent:
6,725,363 →
Application:
09/629,317 →
Using a Centralized Server to Coordinate Assignment of Identifiers in a Distributed System
Patent:
6,735,220 →
Application:
09/629,936 →
Method and System for Integrating Telephone Voice Communications into a Client-Server Architecture
Patent:
6,732,143 →
Application:
09/637,457 →
Method for Efficient Modular Polynomial Division in Finite Fields F(2^M)
Patent:
6,721,771 →
Application:
09/649,356 →
General Data Structure for Describing Logical Data Spaces
Patent:
6,728,722 →
Application:
09/650,370 →
Method and Apparatus for Hybrid Checkpointing
Patent:
6,718,538 →
Application:
09/652,717 →
Fault Tolerant Data Storage System
Patent:
6,732,289 →
Application:
09/652,972 →
Mechanism for Error Handling in a Computer System
Patent:
6,718,460 →
Application:
09/655,258 →
Method and System for Decoding a Row Address to Assert Multiple Adjacent Rows in a Memory Structure
Patent:
6,711,664 →
Application:
09/660,721 →
Method and Apparatus for Controlling a Bus Clock Frequency in Response to a Signal from a Requesting Component
Patent:
6,728,890 →
Application:
09/670,417 →
Method and Apparatus for Controlling Operating Modes of a Phase Locked Loop Circuit Upon Detecting Frequency of the System Clock Being Greater or Lower Than a Preselected Setpoint
Patent:
6,718,473 →
Application:
09/670,420 →
Incorporating Local Branch History When Predicting Multiple Conditional Branch Outcomes
Patent:
6,738,897 →
Application:
09/680,840 →
Method and Apparatus for Configuration Using a Portable Electronic Configuration Device
Patent:
6,738,027 →
Application:
09/691,476 →
Dual Mode (Registered/Unbuffered) Memory Interface
Patent:
6,711,646 →
Application:
09/693,332 →
Apparatus and Method for Applying Multiple Generators to Crc Calculation
Patent:
6,732,317 →
Application:
09/695,619 →
Hardware Architecture for a Multi-Mode Power Management System Using a Constant Time Reference for Operating System Support
Patent:
6,735,707 →
Application:
09/698,427 →
Selectively Enabling Expression Folding During Program Compilation
Patent:
6,728,953 →
Application:
09/703,413 →
Using Feedback to Determine the Size of an Object Cache
Storage Array Interconnection Fabric Using a Torus Topology
Method and Apparatus for Detecting Valid Clock Signals at a Clock Receiver Circuit
Computer-Based List Editor
Patent:
6,717,595 →
Application:
09/752,343 →
Integrated Time Domain Reflectometry (Tdr) Tester
Using Rendering Molecules to Manage Scene-Based Rendering
Spin-Wheel Sdram Access Scheduler for High Performance Microprocessors
Marking Memory Elements Based Upon Usage of Accessed Information During Speculative Execution
Bi-Directional Communication System
Method and Apparatus for Efficiently Broadcasting Transactions Between an Address Repeater and a Client
Multi-Bank Memory Subsystem Employing an Arrangement of Multiple Memory Modules
Patent:
6,725,314 →
Application:
09/823,540 →
Variable Width Parallel Cyclical Redundancy Check
Dynamically Allocated Cache Memory for a Multi-Processor Unit
Efficient Antialiased Dot Rasterization
Memory Module with Equal Driver Loading
Integrated Circuit Chip Test Adapter
A Computer System Employing Multiple Board Sets and Coherence Schemes
Method and Apparatus for Preventing Cache Pollution in Microprocessors with Speculativeaddress Loads
Shield Assignment Using Preferential Shields
Adding Electrical Resistance in Series with Bypass Capacitors Using Annular Resistors
Using Ancillary Geometry for Visibility Determination
Fan Carrier, Computer System and Method of Installing and Removing a Fan in a Computer System
Multiple Address Translations
Method and Apparatus to Facilitate Generating Simulation Modules for Testing System Designs
System and Method for Controlling a Number of Outstanding Data Transactions Within an Integrated Circuit
Apparatus and Methods for Enhancing Thermal Performance of Integrated Circuit Packages
A Cable Management System for Electronic Devices Such Flat Panel Monitors
Low Power Memory Design with Asymmetric Bit Line Driver
(Design Rule Check)/(Electrical Rule Check) Algorithms Using a System Resolution
Backup and Restore of Data Associated with a Host in a Dynamically Changing Virtual Server Farm Without Involement of a Server That Uses an Associated Storage Device
Patent:
6,714,980 →
Application:
10/104,886 →
Fast Lifetime Analysis of Objects in a Garbage-Collected System
On-Chip Decoupling Capacitors Designed for a 0.11 Micron and Beyond Dual Gate Oxide Cmos Technology
Knowledge-Based Intelligent Full Scan Dump Processing Methodology
Method and a System to Distribute Clock Signals in Digital Circuits
Memory Management System Supporting Deletion of Transient Objects
Method and Apparatus for Deleting Objects from Memory Within a Smart Card
Dynamic Modulation of on-Chip Supply Voltage for Low-Power Design
Method and Apparatus to Facilitate Global Routing for an Integrated Circuit Layout
Using an L2 Directory to Facilitate Speculative Loads in a Multiprocessor System
Method and Apparatus for Facilitating Speculative Loads in a Multiprocessor System
Delay Locked Loop Design with Diode for Loop Filter Capacitance Leakage Current Control
Automated Design Rule Violation Correction When Adding Dummy Geometries to a Design Layout
Method and Apparatus for Analyzing Inductive Effects in a Circuit Layout
Sstl Pull-Down Pre-Driver Design Using Regulated Power Supply
Method and Apparatus for Electrostatically Aligning Intergrated Circuits
Patent:
6,710,436 →
Application:
10/317,481 →
Dual Edge-Triggered Flip-Flop Design with Asynchronous Programmable Reset
Patent:
6,720,813 →
Application:
10/390,286 →