Patent Assignment
Reel/Frame 038378/0400
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 9
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAP[ORE, SGX, SINGAPORE
Covered Applications
(84)
PALLET-SIZED SHIPPING AND DISPLAY TRAY
App. No. 15/069,007
→
METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLASMA PROCESSING
App. No. 14/137,352
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE TRACES AND METHOD OF MANUFACTURE THEREOF
App. No. 14/038,577
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SPREADER AND METHOD OF MANUFACTURE THEREOF
App. No. 14/037,110
→
BEAM MECHANICAL COMPRESSION DEVICE
App. No. 14/018,949
→
INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE AND METHOD OF MANUFACTURING THEREOF
App. No. 13/247,890
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/241,141
→
WIRE BOND INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/178,331
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/965,018
→
INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE
App. No. 12/582,587
→
SEMICONDUCTOR PACKAGE HEAT SPREADER
App. No. 12/498,163
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HIGH LEAD COUNT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/484,245
→
STACKED INTEGRATED CIRCUIT LEADFRAME PACKAGE SYSTEM
App. No. 12/236,227
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL CONNECTIVITY
App. No. 11/936,532
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PASSIVE COMPONENTS
App. No. 11/859,462
→
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
App. No. 11/772,776
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INTEGRATED CIRCUIT DIE WITH PEDESTAL
App. No. 11/760,690
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INTEGRATED CIRCUIT PACKAGE WITH LEADFRAME LOCKED ENCAPSULATION AND METHOD OF MANUFACTURE THEREFOR
App. No. 11/697,779
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METHOD OF FABRICATING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED LAND GRID ARRAY (LGA) PACKAGE STACKED OVER BALL GRID ARRAY (BGA) PACKAGE
App. No. 11/626,272
→
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
App. No. 11/536,544
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STIFFENER
App. No. 11/456,544
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DUAL ROW LEADFRAME AND FABRICATION METHOD
App. No. 11/379,740
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METHOD OF FABRICATING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED LAND GRID ARRAY (LGA) PACKAGE STACKED OVER BALL GRID ARRAY (BGA) PACKAGE
App. No. 11/374,378
→
METHOD OF FABRICATING A SEMICONDUCTOR STACKED MULIT-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE
App. No. 11/372,988
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SYSTEM FOR DIFFERENT BOND PADS IN AN INTEGRATED CIRCUIT PACKAGE
App. No. 11/306,352
→
SEMICONDUCTOR PACKAGE WITH PASSIVE DEVICE INTEGRATION
App. No. 11/306,354
→
INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE
App. No. 11/164,329
→
SEMICONDUCTOR PACKAGE FOR A LARGE DIE
App. No. 11/169,850
→
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
App. No. 11/022,375
→
SEMICONDUCTOR PACKAGES AND LEADFRAME ASSEMBLIES
App. No. 10/993,526
→
STACKED SEMICONDUCTOR PACKAGES
App. No. 10/986,510
→
INTEGRATED CIRCUIT PACKAGE
App. No. 10/969,361
→
ARRAY-MOLDED PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR
App. No. 10/921,377
→
SEMICONDUCTOR DEVICE PACKAGE
App. No. 10/914,870
→
METHOD AND APPARATUS FOR STACKED DIE PACKAGING
App. No. 10/913,806
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INTEGRATED CIRCUIT DIE WITH PEDESTAL
App. No. 10/894,561
→
CHIP SCALE PACKAGE WITH OPEN SUBSTRATE
App. No. 10/866,561
→
PACKAGING FOR OPTOELECTRONIC DEVICES
App. No. 10/850,934
→
INTEGRATED CIRCUIT PACKAGE WITH LEADFRAME LOCKED ENCAPSULATION AND METHOD OF MANUFACTURE THEREFOR
App. No. 10/850,220
→
METHOD OF MANUFACTURING DIFFERENT BOND PADS ON THE SAME SUBSTRATE OF AN INTEGRATED CIRCUIT PACKAGE
App. No. 10/846,176
→
DUAL ROW LEADFRAME AND FABRICATION METHOD
App. No. 10/846,171
→
HEAT SPREADER FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
App. No. 10/836,916
→
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
App. No. 10/837,347
→
THERMALLY ENHANCED STACKED DIE PACKAGE AND FABRICATION METHOD
App. No. 10/825,910
→
SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT PACKAGE ON A PRINTED CIRCUIT BOARD
App. No. 10/825,810
→
HEAT SPREADER ANCHORING AND GROUNDING METHOD AND THERMALLY ENHANCED PBGA PACKAGE USING THE SAME
App. No. 10/804,732
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SEMICONDUCTOR PACKAGE WITH PASSIVE DEVICE INTEGRATION
App. No. 10/773,716
→
STRIP-FABRICATED FLIP CHIP IN PACKAGE AND FLIP CHIP IN SYSTEM HEAT SPREADER ASSEMBLIES AND FABRICATION METHODS THEREFOR
App. No. 10/766,746
→
HEAT SPREADER INTERCONNECT FOR THERMALLY ENHANCED PBGA PACKAGES
App. No. 10/765,644
→
MULTI-PACKAGE CONVERSION KIT FOR A PICK AND PLACE HANDLER
App. No. 10/745,149
→
FLIP CHIP MOLDED/EXPOSED DIE PROCESS AND PACKAGE STRUCTURE
App. No. 10/693,217
→
METHOD FOR FABRICATING SEMICONDUCTOR PACKAGES, AND LEADFRAME ASSEMBLIES FOR THE FABRICATION THEREOF
App. No. 10/682,273
→
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED LAND GRID ARRAY (LGA) PACKAGE STACKED OVER BALL GRID ARRAY (BGA) PACKAGE
App. No. 10/681,735
→
SEMICONDUCTOR STACKED MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE
App. No. 10/681,572
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STACKED SEMICONDUCTOR PACKAGES AND METHOD FOR THE FABRICATION THEREOF
App. No. 10/676,736
→
METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE FOR A DIE LARGER THAN A DIE PAD
App. No. 10/606,429
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GROUND PLANE FOR EXPOSED PACKAGE
App. No. 10/462,264
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SEMICONDUCTOR PACKAGE WITH HEAT SINK
App. No. 10/462,288
→
SYSTEM FOR SEMICONDUCTOR PACKAGE WITH STACKED DIES
App. No. 10/463,007
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MOISTURE RESISTANT INTEGRATED CIRCUIT LEADFRAME PACKAGE
App. No. 10/446,275
→
INTEGRATED CIRCUIT LEADFRAME WITH GROUND PLANE
App. No. 10/444,849
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HEAT SPREADERS, HEAT SPREADER PACKAGES, AND FABRICATION METHODS FOR USE WITH FLIP CHIP SEMICONDUCTOR DEVICES
App. No. 10/434,256
→
SINGLE UNIT AUTOMATED ASSEMBLY OF FLEX ENHANCED BALL GRID ARRAY PACKAGES
App. No. 10/371,515
→
THERMALLY ENHANCED STACKED DIE PACKAGE
App. No. 10/359,407
→
SUPER THIN/SUPER THERMAL BALL GRID ARRAY PACKAGE
App. No. 10/339,158
→
ENHANCED BGA GROUNDED HEATSINK
App. No. 10/323,447
→
MOLD CAP ANCHORING METHOD FOR MOLDED FLEX BGA PACKAGES
App. No. 10/315,533
→
COST EFFECTIVE SUBSTRATE FABRICATION FOR FLIP-CHIP PACKAGES
App. No. 10/279,900
→
LEADFRAME FOR DIE STACKING APPLICATIONS AND RELATED DIE STACKING CONCEPTS
App. No. 10/256,407
→
INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREFOR
App. No. 10/251,231
→
PBGA SINGULATED SUBSTRATE FOR MODEL MELAMINE CLEANING
App. No. 10/236,579
→
METHOD OF TRIMMING AND SINGULATING LEADED SEMICONDUCTOR PACKAGES
App. No. 10/236,650
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TEST COUPON PATTERN DESIGN TO CONTROL MULTILAYER SAW SINGULATED PLASTIC BALL GRID ARRAY SUBSTRATE MIS-REGISTRATION
App. No. 10/224,151
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A METHOD OF FORMING A SMALL PITCH TORCH BUMP FOR MOUNTING HIGH-PERFORMANCE FLIP-FLOP DEVICES
App. No. 10/151,977
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TESTING OF BGA AND OTHER CSP PACKAGES USING PROBING TECHNIQUES
App. No. 10/140,573
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HEAT SPREADER INTERCONNECT METHODOLOGY FOR THERMALLY ENHANCED PBGA PACKAGES
App. No. 10/119,920
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HEAT SPREADER HOLE PIN 1 IDENTIFIER
App. No. 10/099,284
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GROUND PLANE FOR EXPOSED PACKAGE
App. No. 10/083,993
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HEAT SPREADER ANCHORING & GROUNDING METHOD & THERMALLY ENHANCED PBGA PACKAGE USING THE SAME
App. No. 10/055,094
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MOLDED STIFFENER FOR FLEXIBLE CIRCUIT MOLDING
App. No. 10/043,603
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PBGA SUBSTRATE FOR ANCHORING HEAT SINK
App. No. 09/961,555
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PLASTIC BALL GRID ARRAY PACKAGE WITH INTEGRAL HEATSINK
App. No. 09/919,763
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METHOD AND APPARATUS FOR ESTABLISHING QUICK AND RELIABLE CONNECTION BETWEEN A SEMICONDUCTOR DEVICE HANDLER PLATE AND A SEMICONDUCTOR DEVICE TEST HEAD PLATE
App. No. 09/828,677
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PROCESS AND SUPPORT CARRIER FOR FLEXIBLE SUBSTRATES
App. No. 09/759,904
→