IP Library Granted Patent US 9,093,392
Granted Patent B2
US 9,093,392 · App. 12/965,018 · Granted Jul 28, 2015

Integrated circuit packaging system with vertical interconnection and method of manufacture thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,093,392
App. No.
12/965,018
Granted
Jul 28, 2015
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window; mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side; attaching a lower internal connector to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window; forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side; and forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a peripheral connector bottom side directly on the package substrate top side and a peripheral connector top side coplanar with the upper insulation top side.

Claims (46)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window;

mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side;

attaching a lower internal connector to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window;

forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side above the base integrated circuit, the upper insulation having an upper insulation cavity at the upper insulation top side and in the upper insulation, wherein the upper insulation cavity provides spacing for mounting a top package within the upper insulation cavity and over the base integrated circuit;

forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a straight non-horizontal side within the upper insulation, a peripheral connector bottom side directly on the package substrate top side, and a peripheral connector top side coplanar with the upper insulation top side, wherein the base integrated circuit is below the peripheral connector top side and exposed from the upper insulation within the upper insulation cavity; and

mounting a top structure, having a top substrate, on the peripheral through-insulation connector, a top component attached to a top substrate bottom side of the top structure and partially within the upper insulation cavity.

2. The method as claimed in claim 1 wherein forming the upper insulation includes forming the upper insulation having the upper insulation cavity exposing the base inactive side.

3. The method as claimed in claim 1 further comprising forming a central through-insulation connector through the upper insulation and over the base inactive side.

4. The method as claimed in claim 1 wherein forming the upper insulation includes forming the upper insulation with the base inactive side fully exposed from the upper insulation.

5. The method as claimed in claim 1 further comprising attaching a stack structure to the peripheral connector top side.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window;

mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side;

attaching a lower internal connector to the base active side and the package substrate bottom side;

forming a lower insulation over the lower internal connector and the base integrated circuit;

forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side above the base integrated circuit, the upper insulation having an upper insulation cavity at the upper insulation top side and in the upper insulation, wherein the upper insulation cavity provides spacing for mounting a top package within the upper insulation cavity and over the base integrated circuit;

forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a straight non-horizontal side within the upper insulation, a peripheral connector bottom side directly on the package substrate top side, and a peripheral connector top side coplanar with the upper insulation top side, wherein the base integrated circuit is below the peripheral connector top side and exposed from the upper insulation within the upper insulation cavity; and

mounting a top structure, having a top substrate, on the peripheral through-insulation connector, a top component attached to a top substrate bottom side of the top structure and partially within the upper insulation cavity.

7. The method as claimed in claim 6 further comprising connecting a stack integrated circuit to the base integrated circuit.

8. The method as claimed in claim 6 wherein mounting the top structure having the top component includes mounting the to structure over the upper insulation cavity.

9. The method as claimed in claim 6 wherein mounting the top structure having the top substrate bottom side on the peripheral through-insulation connector includes mounting the top structure with a top component active side connected to the top substrate bottom side, and a top component inactive side facing the base integrated circuit.

10. The method as claimed in claim 6 wherein mounting the top structure having the top substrate bottom side on the peripheral through-insulation connector includes mounting the top structure with a top component inactive side attached to the top substrate bottom side, and a top component active side facing the base integrated circuit.

11. An integrated circuit packaging system comprising:

a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window;

a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side;

a lower internal connector attached to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window;

an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side above the base integrated circuit, the upper insulation having an upper insulation cavity at the upper insulation top side and in the upper insulation, wherein the upper insulation cavity provides spacing for mounting a top package within the upper insulation cavity and over the base integrated circuit;

a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a straight non-horizontal side within the upper insulation, a peripheral connector bottom side directly on the package substrate top side, and a peripheral connector top side coplanar with the upper insulation top side, wherein the base integrated circuit is below the peripheral connector top side and exposed from the upper insulation within the upper insulation cavity;

a top structure, having a top substrate, connected to the peripheral through-insulation connector; and

a top component attached to a to substrate bottom side of the top structure and partially within the upper insulation cavity.

12. The system as claimed in claim 11 wherein the upper insulation includes the upper insulation cavity exposing the base inactive side.

13. The system as claimed in claim 11 further comprising a central through-insulation connector through the upper insulation and over the base inactive side.

14. The system as claimed in claim 11 wherein the upper insulation fully exposes the base inactive side.

15. The system as claimed in claim 11 further comprising a stack structure attached to the peripheral connector top side.

16. The system as claimed in claim 11 further comprising a lower insulation over the lower internal connector and the base integrated circuit.

17. The system as claimed in claim 16 further comprising a stack integrated circuit connected to the base integrated circuit.

18. The system as claimed in claim 16 wherein the top structure and the top component are over the upper insulation cavity.

19. The system as claimed in claim 16 wherein:

the top substrate has the top substrate bottom side over the peripheral through-insulation connector;

a top component active side of the top component is connected to the top substrate bottom side; and

a top component inactive side of the top component is facing the base integrated circuit.

20. The system as claimed in claim 16 wherein:

the top substrate has the top substrate bottom side over the peripheral through-insulation connector;

a top component inactive side of the top component is attached to the top substrate bottom side; and

a top component active side of the top component is facing the base integrated circuit.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0400. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064806/0593 →
RELEASE OF SECURITY INTEREST Recorded Jun 16, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052950/0497 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →