Patent Assignment
Reel/Frame 052950/0497
RELEASE OF SECURITY INTEREST
Recorded: 2020-06-16
Received: 2020-06-16
Pages: 27
Assignor
CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Executed: 2019-05-03
Assignees
STATS CHIPPAC, INC.
46429 LANDING PARKWAY, FREMONT, CA, 94538, UNITED STATES
STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Applications
(88)
Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die
App. No. 14/596,080
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE TRACES AND METHOD OF MANUFACTURE THEREOF
App. No. 14/038,577
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SPREADER AND METHOD OF MANUFACTURE THEREOF
App. No. 14/037,110
→
Bump-on-Lead Flip Chip Interconnection
App. No. 13/965,356
→
Flip Chip Interconnect Solder Mask
App. No. 13/596,860
→
FLIP CHIP INTERCONNECT SOLDER MASK
App. No. 13/596,446
→
Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package
App. No. 13/268,048
→
INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE AND METHOD OF MANUFACTURING THEREOF
App. No. 13/247,890
→
SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD OF FORMING METALLURGICAL INTERCONNECTION DIRECTLY BETWEEN A DUP AND METALLIZATION ON A SUBTRATE
App. No. 13/245,181
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/241,141
→
WIRE BOND INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/178,331
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/965,018
→
INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE
App. No. 12/582,587
→
SEMICONDUCTOR PACKAGE HEAT SPREADER
App. No. 12/498,163
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HIGH LEAD COUNT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/484,245
→
Apparatus and process for precise encapsulation of flip chip interconnects
App. No. 12/018,441
→
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
App. No. 11/772,776
→
INTEGRATED CIRCUIT DIE WITH PEDESTAL
App. No. 11/760,690
→
INTEGRATED CIRCUIT PACKAGE WITH LEADFRAME LOCKED ENCAPSULATION AND METHOD OF MANUFACTURE THEREFOR
App. No. 11/697,779
→
METHOD OF FABRICATING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED LAND GRID ARRAY (LGA) PACKAGE STACKED OVER BALL GRID ARRAY (BGA) PACKAGE
App. No. 11/626,272
→
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
App. No. 11/536,544
→
DUAL ROW LEADFRAME AND FABRICATION METHOD
App. No. 11/379,740
→
METHOD OF FABRICATING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED LAND GRID ARRAY (LGA) PACKAGE STACKED OVER BALL GRID ARRAY (BGA) PACKAGE
App. No. 11/374,378
→
METHOD OF FABRICATING A SEMICONDUCTOR STACKED MULIT-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE
App. No. 11/372,988
→
Semiconductor multi-package module having inverted second package stacked over die-down flip-chip ball grid array (BGA) package
App. No. 11/337,168
→
SEMICONDUCTOR PACKAGE WITH PASSIVE DEVICE INTEGRATION
App. No. 11/306,354
→
INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE
App. No. 11/164,329
→
SEMICONDUCTOR PACKAGE FOR A LARGE DIE
App. No. 11/169,850
→
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
App. No. 11/022,375
→
SEMICONDUCTOR PACKAGES AND LEADFRAME ASSEMBLIES
App. No. 10/993,526
→
STACKED SEMICONDUCTOR PACKAGES
App. No. 10/986,510
→
INTEGRATED CIRCUIT PACKAGE
App. No. 10/969,361
→
ARRAY-MOLDED PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR
App. No. 10/921,377
→
SEMICONDUCTOR DEVICE PACKAGE
App. No. 10/914,870
→
METHOD AND APPARATUS FOR STACKED DIE PACKAGING
App. No. 10/913,806
→
INTEGRATED CIRCUIT DIE WITH PEDESTAL
App. No. 10/894,561
→
CHIP SCALE PACKAGE WITH OPEN SUBSTRATE
App. No. 10/866,561
→
PACKAGING FOR OPTOELECTRONIC DEVICES
App. No. 10/850,934
→
INTEGRATED CIRCUIT PACKAGE WITH LEADFRAME LOCKED ENCAPSULATION AND METHOD OF MANUFACTURE THEREFOR
App. No. 10/850,220
→
DUAL ROW LEADFRAME AND FABRICATION METHOD
App. No. 10/846,171
→
HEAT SPREADER FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
App. No. 10/836,916
→
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
App. No. 10/837,347
→
THERMALLY ENHANCED STACKED DIE PACKAGE AND FABRICATION METHOD
App. No. 10/825,910
→
HEAT SPREADER ANCHORING AND GROUNDING METHOD AND THERMALLY ENHANCED PBGA PACKAGE USING THE SAME
App. No. 10/804,732
→
SEMICONDUCTOR PACKAGE WITH PASSIVE DEVICE INTEGRATION
App. No. 10/773,716
→
STRIP-FABRICATED FLIP CHIP IN PACKAGE AND FLIP CHIP IN SYSTEM HEAT SPREADER ASSEMBLIES AND FABRICATION METHODS THEREFOR
App. No. 10/766,746
→
HEAT SPREADER INTERCONNECT FOR THERMALLY ENHANCED PBGA PACKAGES
App. No. 10/765,644
→
MULTI-PACKAGE CONVERSION KIT FOR A PICK AND PLACE HANDLER
App. No. 10/745,149
→
FLIP CHIP MOLDED/EXPOSED DIE PROCESS AND PACKAGE STRUCTURE
App. No. 10/693,217
→
METHOD FOR FABRICATING SEMICONDUCTOR PACKAGES, AND LEADFRAME ASSEMBLIES FOR THE FABRICATION THEREOF
App. No. 10/682,273
→
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED LAND GRID ARRAY (LGA) PACKAGE STACKED OVER BALL GRID ARRAY (BGA) PACKAGE
App. No. 10/681,735
→
SEMICONDUCTOR STACKED MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE
App. No. 10/681,572
→
STACKED SEMICONDUCTOR PACKAGES AND METHOD FOR THE FABRICATION THEREOF
App. No. 10/676,736
→
METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE FOR A DIE LARGER THAN A DIE PAD
App. No. 10/606,429
→
GROUND PLANE FOR EXPOSED PACKAGE
App. No. 10/462,264
→
SEMICONDUCTOR PACKAGE WITH HEAT SINK
App. No. 10/462,288
→
SYSTEM FOR SEMICONDUCTOR PACKAGE WITH STACKED DIES
App. No. 10/463,007
→
MOISTURE RESISTANT INTEGRATED CIRCUIT LEADFRAME PACKAGE
App. No. 10/446,275
→
INTEGRATED CIRCUIT LEADFRAME WITH GROUND PLANE
App. No. 10/444,849
→
HEAT SPREADERS, HEAT SPREADER PACKAGES, AND FABRICATION METHODS FOR USE WITH FLIP CHIP SEMICONDUCTOR DEVICES
App. No. 10/434,256
→
SINGLE UNIT AUTOMATED ASSEMBLY OF FLEX ENHANCED BALL GRID ARRAY PACKAGES
App. No. 10/371,515
→
THERMALLY ENHANCED STACKED DIE PACKAGE
App. No. 10/359,407
→
SUPER THIN/SUPER THERMAL BALL GRID ARRAY PACKAGE
App. No. 10/339,158
→
ENHANCED BGA GROUNDED HEATSINK
App. No. 10/323,447
→
MOLD CAP ANCHORING METHOD FOR MOLDED FLEX BGA PACKAGES
App. No. 10/315,533
→
COST EFFECTIVE SUBSTRATE FABRICATION FOR FLIP-CHIP PACKAGES
App. No. 10/279,900
→
LEADFRAME FOR DIE STACKING APPLICATIONS AND RELATED DIE STACKING CONCEPTS
App. No. 10/256,407
→
INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREFOR
App. No. 10/251,231
→
PBGA SINGULATED SUBSTRATE FOR MODEL MELAMINE CLEANING
App. No. 10/236,579
→
METHOD OF TRIMMING AND SINGULATING LEADED SEMICONDUCTOR PACKAGES
App. No. 10/236,650
→
TEST COUPON PATTERN DESIGN TO CONTROL MULTILAYER SAW SINGULATED PLASTIC BALL GRID ARRAY SUBSTRATE MIS-REGISTRATION
App. No. 10/224,151
→
A METHOD OF FORMING A SMALL PITCH TORCH BUMP FOR MOUNTING HIGH-PERFORMANCE FLIP-FLOP DEVICES
App. No. 10/151,977
→
TESTING OF BGA AND OTHER CSP PACKAGES USING PROBING TECHNIQUES
App. No. 10/140,573
→
TESTING OF BGA AND OTHER CSP PACKAGES USING PROBING TECHNIQUES
App. No. 10/140,572
→
HEAT SPREADER INTERCONNECT METHODOLOGY FOR THERMALLY ENHANCED PBGA PACKAGES
App. No. 10/119,920
→
SEMICONDUCTOR PACKAGE HAVING HEAT SINK ATTACHED TO PRE-MOLDED CAVITIES AND METHOD FOR CREATING THE PACKAGE
App. No. 10/116,983
→
HEAT SPREADER HOLE PIN 1 IDENTIFIER
App. No. 10/099,284
→
GROUND PLANE FOR EXPOSED PACKAGE
App. No. 10/083,993
→
HEAT SPREADER ANCHORING & GROUNDING METHOD & THERMALLY ENHANCED PBGA PACKAGE USING THE SAME
App. No. 10/055,094
→
MOLDED STIFFENER FOR FLEXIBLE CIRCUIT MOLDING
App. No. 10/043,603
→
PBGA SUBSTRATE FOR ANCHORING HEAT SINK
App. No. 09/961,555
→
DIE PADDLE ENHANCEMENT FOR EXPOSED PAD IN SEMICONDUCTOR PACKAGING
App. No. 09/920,599
→
PLASTIC BALL GRID ARRAY PACKAGE WITH INTEGRAL HEATSINK
App. No. 09/919,763
→
FLIP CHIP THERMALLY ENHANCED BALL GRID ARRAY
App. No. 09/877,324
→
SUPER THIN/SUPER THERMAL BALL GRID ARRAY PACKAGE
App. No. 09/867,095
→
ENHANCED BGA GROUNDED HEATSINK
App. No. 09/849,671
→
METHOD AND APPARATUS FOR ESTABLISHING QUICK AND RELIABLE CONNECTION BETWEEN A SEMICONDUCTOR DEVICE HANDLER PLATE AND A SEMICONDUCTOR DEVICE TEST HEAD PLATE
App. No. 09/828,677
→
PROCESS AND SUPPORT CARRIER FOR FLEXIBLE SUBSTRATES
App. No. 09/759,904
→