Patent Assignment
Reel/Frame 039050/0613
Assignment of Assignor's Interest
Recorded: 2016-06-30
Pages: 6
Assignors
GUPTA, UMESH
Executed: 2016-06-02
TRIPATHI, SHASHANK
Executed: 2016-05-30
KUMAR, NARESH
Executed: 2016-05-30
VEERAVALLI, ARVIND NEMBILI
Executed: 2016-06-08
SETHIA, PRASHANT
Executed: 2016-06-06
GOVILA, RITIKA
Executed: 2016-06-08
Assignee
CADENCE DESIGN SYSTEM
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Method and Apparatus for Performing Sign-Off Timing Analysis of Circuit Designs Using Inter-Power Domain Logic
Patent:
10,114,920 →
Application:
15/197,142 →