Patent Assignment
Reel/Frame 039058/0909
Assignment of Assignor's Interest
Recorded: 2016-06-30
Pages: 9
Assignors
LOH, LAWRENCE
Executed: 2016-06-17
COSTA, ARTUR MELO MOTA
Executed: 2016-06-20
GUIMARAES, BRENO RODRIGUES
Executed: 2016-06-20
PEIXOTO, FABIANO
Executed: 2016-06-20
TAVARES, ANDREA IABRUDI
Executed: 2016-06-20
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Methods, Systems, and Articles of Manufacture for Verifying an Electronic Design Using Hierarchical Clock Domain Crossing Verification Techniques
Patent:
10,204,201 →
Application:
15/199,059 →