Patent Assignment
Reel/Frame 039061/0239
Assignment of Assignor's Interest
Recorded: 2016-06-30
Pages: 6
Assignors
LI, NAN
Executed: 2016-06-28
TSENG, HING KEY KENNETH
Executed: 2016-06-28
CUI, SHUPENG
Executed: 2016-06-28
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Methods, Systems, and Articles of Manufacture for Implementing an Electronic Design with Transistor Level Satisfiability Models
Patent:
10,402,525 →
Application:
15/199,854 →