Patent Assignment
Reel/Frame 039694/0849
Assignment of Assignor's Interest
Recorded: 2016-09-10
Pages: 3
Assignor
HUANG, YI-CHIEH
Executed: 2016-08-29
Assignee
MEDIATEK INC.
NO. 1, DUSING RD. 1ST, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN
Covered Property
(1)
Clock Generator Using Resistive Components to Generate Sub-Gate Delays and/or Using Common-Mode Voltage Based Frequency-Locked Loop Circuit for Frequency Offset Reduction