Patent Assignment
Reel/Frame 039722/0808
Assignment of Assignor's Interest
Recorded: 2016-09-13
Pages: 9
Assignors
SHARMA, AMIT
Executed: 2016-08-23
AGGARWAL, AMIT
Executed: 2016-08-23
DUA, AMIT
Executed: 2016-08-24
CHOPRA, MANU
Executed: 2016-08-24
REYNOLDS, VINCENT
Executed: 2016-08-24
RAHEJA, ABHISHEK
Executed: 2016-08-24
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Debugging Failures in X-Propagation Logic Circuit Simulation
Patent:
10,325,042 →
Application:
15/247,798 →