IP Library › Assignment 039761/0908
Patent Assignment
Reel/Frame 039761/0908

Assignment of Assignor's Interest

Recorded: 2016-09-16 Pages: 5
Assignors
ANANTHAKRISHNAN, AVINASH N.
Executed: 2016-09-06
SHRALL, JEREMY J.
Executed: 2016-08-29
SURYANARAYANAN, ANUPAMA
Executed: 2016-09-12
AMBARDEKAR, AMEYA
Executed: 2016-08-29
TOPPER, CRAIG
Executed: 2016-08-29
HEIT, ERIC R.
Executed: 2016-08-29
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Property (1)
Processor To Pre-Empt Voltage Ramps For Exit Latency Reductions
Application: 15/252,529 →
Publication: US 2018/0060085
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Corrective Assignment to Correct the Inventor Joseph M. Alberts Name Missing in the Assignment Document. Previously Recorded at Reel: 039761 Frame: 0908. Assignor(S) Hereby Confirms the Assignment . Sep 23, 2016
From: ANANTHAKRISHNAN, AVINASH N.; SHRALL, JEREMY J.; SURYANARAYANAN, ANUPAMA; AMBARDEKAR, AMEYA
To: INTEL CORPORATION
Reel/Frame 040125/0072 →