Patent Assignment
Reel/Frame 040908/0979
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2016-12-14
Received: 2016-12-14
Pages: 11
Assignor
CYPRESS SEMICONDUCTOR CORPORATION
Executed: 2016-12-09
Assignee
MONTEREY RESEARCH, LLC
3945 FREEDOM CIRCLE, SUITE 900, SANTA CLARA, CA, 95054, UNITED STATES
Covered Applications
(45)
FLOATING GATE MEMORY DEVICE WITH INCREASED COUPLING COEFFICIENT
App. No. 12/154,584
→
CIRCUIT AND METHOD TO INCREASE READ MARGIN IN NON-VOLATILE MEMORIES USING A DIFFERENTIAL SENSING CIRCUIT
App. No. 12/059,560
→
POWER SUPPLY VOLTAGE REGULATOR CIRCUIT AND MICROCOMPUTER
App. No. 12/043,506
→
DUMMY CELL FOR MEMORY CIRCUITS
App. No. 12/006,224
→
3T HIGH DENSITY NVDRAM CELL
App. No. 12/006,227
→
ARCHITECTURE OF A NVDRAM ARRAY AND ITS SENSE REGIME
App. No. 12/006,226
→
DEVICE HAVING A PROTECTIVE CAP FORMED OVER AN ANTI-REFLECTIVE COATING LAYER AND OVER AN INSULATING MATERIAL
App. No. 11/781,551
→
Coupling coefficient for floating gate memory devices
App. No. 60/931,701
→
Method to Double The Read Margin in Non-Volatile Memories by Differential Sensing ARchitecture
App. No. 60/909,362
→
NON-VOLATILE, STATIC RANDOM ACCESS MEMORY WITH REGULATED ERASE SATURATION AND PROGRAM WINDOW
App. No. 11/644,196
→
VARIABLE IMPEDANCE SENSE ARCHITECTURE AND METHOD
App. No. 11/540,831
→
Non-volatile, static random access memory with regulated erase saturation and program window
App. No. 60/838,694
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PULSE WIDTH MODULATION CIRCUIT
App. No. 11/494,620
→
Variable impedance sense architecture and method
App. No. 60/722,612
→
COMMUNICATION DATA CONTROLLER
App. No. 11/169,747
→
MICROCONTROLLER
App. No. 11/168,448
→
IMPEDANCE BUFFER AND METHOD
App. No. 11/138,823
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SIGNAL DETECTION METHOD, FREQUENCY DETECTION METHOD, POWER CONSUMPTION CONTROL METHOD, SIGNAL DETECTING DEVICE, FREQUENCY DETECTING DEVICE, POWER CONSUMPTION CONTROL DEVICE AND ELECTRONIC APPARATUS
App. No. 11/122,123
→
HIGH K STACK FOR NON-VOLATILE MEMORY
App. No. 11/086,310
→
Reference cell configuration for a 1T/1C ferroelectric memory
App. No. 10/993,202
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SEMICONDUCTOR CONTACT AND NITRIDE SPACER FORMATION SYSTEM AND METHOD
App. No. 10/934,923
→
Generic programmable impedance architecture for high speed output buffers
App. No. 60/598,360
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DC component cancellation circuit
App. No. 10/850,395
→
AVOIDING FIELD OXIDE GOUGING IN SHALLOW TRENCH ISOLATION (STI) REGIONS
App. No. 10/799,413
→
AMPLIFICATION CIRCUIT AND OPTICAL COMMUNICATION APPARATUS PROVIDED WITH THE AMPLIFICATION CIRCUIT
App. No. 10/418,174
→
COLUMN DECODER CONFIGURATION FOR A 1T/1C MEMORY
App. No. 10/389,276
→
REDUCED SILICON GOUGING AND COMMON SOURCE LINE RESISTANCE IN SEMICONDUCTOR DEVICES
App. No. 10/358,756
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PULSE WIDTH DETECTION CIRCUIT FILTERING THE INPUT SIGNAL AND GENERATING A BINARY SIGNAL
App. No. 10/327,094
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MOCVD FORMATION OF CU2S
App. No. 10/305,889
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HARD MASK REMOVAL PROCESS INCLUDING ISOLATION DIELECTRIC REFILL
App. No. 10/165,837
→
REPLACING A FIRST LINER LAYER WITH A THICKER OXIDE LAYER WHEN FORMING A SEMICONDUCTOR DEVICE
App. No. 10/126,841
→
ISOLATION TRENCH FILL PROCESS
App. No. 10/120,116
→
CONTACT STRUCTURE AND METHOD OF MAKING THE SAME
App. No. 10/112,572
→
METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
App. No. 10/109,526
→
PLANARIZATION OF A POLYSILICON LAYER SURFACE BY CHEMICAL MECHANICAL POLISH TO IMPROVE LITHOGRAPHY AND SILICIDE FORMATION
App. No. 10/067,765
→
METHOD OF MANUFACTURING HIGH VOLTAGE TRANSISTOR WITH MODIFIED FIELD IMPLANT MASK
App. No. 10/044,510
→
METHOD OF DETERMINING GATE OXIDE THICKNESS OF AN OPERATIONAL MOSFET
App. No. 10/017,832
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INNOVATIVE METHOD OF HARD MASK REMOVAL
App. No. 10/045,354
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METHOD OF FORMING ZERO MARKS
App. No. 09/884,204
→
METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE
App. No. 09/875,073
→
NON-VOLATILE STATIC MEMORY CELL
App. No. 09/871,172
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NAND STACK EEPROM WITH RANDOM PROGRAMMING CAPABILITY
App. No. 09/681,314
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METHOD FOR FABRICATING A CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR DEVICE
App. No. 09/805,287
→
Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer
App. No. 09/799,469
→
SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
App. No. 09/764,223
→