Floating gate memory device with increased coupling coefficient

1. A device comprising an MOS capacitor including a gate structure disposed upon an insulating layer on a substrate, the gate structure comprising a contiguous conductive layer patterned to form a plurality of gate fingers, each gate finger electrically connected to each other through the conductive layer and comprising a length L and a width W less than length L, and a plurality of source/drain diffusions formed in the substrate on each side of the plurality of gate fingers and extending substantially the entire length L of each gate finger, the plurality of source/drain diffusions are separated from each other by channel regions underlying each of the plurality of gate fingers,

wherein the gate structure and the plurality of source/drain diffusions capacitively couple along the length of each of the plurality of gate fingers and a sum of a capacitance formed between the plurality of gate fingers and the source/drain diffusions formed on either side thereof is greater than a sum of a capacitance formed between a continuous conductive region under each gate finger and the overlying gate finger.

2. The device of claim 1 , further comprising ion-implanted tips extending each of the plurality of source/drain diffusions under adjacent gate fingers.

3. The device of claim 2 , wherein the ion-implanted tips extend substantially the entire length L of each gate finger.

4. The device of claim 3 , wherein the ion-implanted tips on each side of each gate finger form the continuous conductive region under the gate finger.

5. The device of claim 4 , wherein the ion-implanted tips and each of the overlying gate fingers are configured to capacitively couple through the insulating layer.

6. The device of claim 1 , wherein the width of each gate finger is substantially uniform along the length thereof.

7. The device of claim 1 , further comprising an MOS tunnel diode coupled with the gate structure to form a floating gate memory device.

8. The device of claim 1 , wherein the gate finger structure substantially does not include an insulator formed on sidewalls of the plurality of gate fingers.

9. A method comprising:

patterning a conductive layer on an insulating layer disposed upon a substrate to form a gate structure comprising a plurality of gate fingers electrically connected to each other through the conductive layer, each gate finger comprising a length L and a width W less than length L; and

forming a plurality of source/drain diffusions in the substrate on each side of the plurality of gate fingers and extending substantially the entire length L of each gate finger, wherein the plurality of source/drain diffusions are separated from each other by channel regions underlying each of the plurality of gate fingers,

wherein the length L and width W or each gate finger are configured so that a sum of a capacitance formed between the plurality of gate fingers and the source/drain diffusions formed on either side thereof is greater than a sum of a capacitance formed between a continuous conductive region under each gate finger and the overlying gate finger.

10. The method of claim 9 , further comprising forming ion-implanted tips extending each of the plurality of source/drain diffusions under adjacent gate fingers, wherein a pair of ion-implanted tips under each gate finger comprises a continuous conductive region under the gate finger.

11. The method of claim 10 , wherein the ion-implanted tips extend substantially the entire length L of each gate finger.

12. The method of claim 11 , wherein the ion-implanted tips on each side of each gate finger form a continuous conductive region under the gate finger.

13. The method of claim 9 , further comprising forming a plurality of contacts to the plurality of source/drain diffusions including forming at least one contact to each source/drain diffusion between each of the plurality of gate fingers.

14. The method of claim 9 , wherein the width of each gate finger is substantially uniform along the length thereof.

15. The method of claim 9 , further comprising coupling the plurality of gate fingers to a tunnel diode to form a floating gate memory device.

16. The method of claim 9 , further comprising coupling the plurality of gate fingers to a tunnel diode to form a floating gate memory device.

17. A MOS capacitor comprising:

a gate structure disposed upon an insulating layer on a substrate, the gate structure comprising a contiguous conductive layer patterned to form a plurality of gate fingers, each gate finger comprising a length L and wherein each gate finger comprises a width W less than length L, wherein the plurality of gate fingers are parallel to each other along the lengths thereof;

a plurality of source/drain diffusions formed in the substrate on each side of the plurality of gate fingers and extending substantially the entire length L of each gate finger, wherein the plurality of source/drain diffusions are separated from each other by channel regions underlying each of the plurality of gate fingers; and

a plurality of contacts to the plurality of source/drain diffusions including at least one contact to each source/drain diffusion located between each of the plurality of gate fingers,

wherein the gate structure and the plurality of source/drain diffusions capacitively couple along the length of each of the plurality of gate fingers and a sum of a capacitance formed between the plurality of gate fingers and the source/drain diffusions formed on either side thereof is greater than a sum of a capacitance formed between a continuous conductive region under each gate finger and the overlying gate finger.

18. The MOS capacitor of claim 17 , wherein the gate finger structure substantially does not include an insulator formed on sidewalls of the plurality of gate fingers.

19. A floating gate memory device comprising the MOS capacitor of claim 17 , and further comprising an MOS tunnel diode coupled with the gate structure.