Patent Assignment
Reel/Frame 041029/0354
Assignment of Assignor's Interest
Recorded: 2017-01-20
Pages: 5
Assignors
WU, YUN-LIN
Executed: 2017-01-16
KUO, CHENG-CHENG
Executed: 2017-01-16
CHIANG, CHIA-PING
Executed: 2017-01-16
HSU, CHIH-WEI
Executed: 2017-01-16
LIN, HUA-TAI
Executed: 2017-01-17
CHEN, KUEI-SHUN
Executed: 2017-01-17
LUNG, YUAN-HSIANG
Executed: 2017-01-16
TSAI, YAN-TSO
Executed: 2017-01-17
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
NO. 8, LI-HSIN RD. 6, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, 300-77, TAIWAN
Covered Property
(1)
Method for Improving Circuit Layout for Manufacturability