Patent Assignment
Reel/Frame 041238/0341
Assignment of Assignor's Interest
Recorded: 2017-02-13
Pages: 9
Assignors
BHATI, ISHWAR S.
Executed: 2017-01-30
LIU, HUICHU
Executed: 2017-01-26
GAUR, JAYESH
Executed: 2017-01-30
KORGAONKAR, KUNAL
Executed: 2017-01-31
MANIPATRUNI, SASIKANTH
Executed: 2017-02-06
SUBRAMONEY, SREENIVAS
Executed: 2017-02-03
KARNIK, TANAY
Executed: 2017-01-25
WANG, HONG
Executed: 2017-01-31
YOUNG, IAN A.
Executed: 2017-02-10
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Property
(1)
Write Congestion Aware Bypass for Non-Volatile Memory, Last Level Cache (Llc) Dropping from Write Queue Responsive to Write Queue Being Full and Read Queue Threshold Wherein the Threshold Is Derived from Latency of Write to Llc and Main Memory Retrieval Time