IP Library Assignment 041696/0124
Patent Assignment
Reel/Frame 041696/0124

Assignment of Assignor's Interest

Recorded: 2017-03-23 Pages: 10
Assignors
VRUDHULA, SARMA
Executed: 2017-02-28
DAVIS, JOSEPH
Executed: 2017-03-22
KULKARNI, NIRANJAN
Executed: 2017-03-22
DENGI, AYKUT
Executed: 2017-02-28
Assignee
ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
1475 NORTH SCOTTSDALE ROAD, SKYSONG - SUITE 200, SCOTTSDALE, ARIZONA, 85257
Covered Property (1)
Method of Obfuscating Digital Logic Circuits Using Threshold Voltage
Patent: 9,876,503 →
Application: 15/390,970 →
Publication: US 2017/0187382
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Confirmatory License Feb 27, 2017
From: ARIZONA STATE UNIVERSITY, TEMPE
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 041823/0073 →