Patent Assignment
Reel/Frame 041968/0499
Assignment of Assignor's Interest
Recorded: 2017-04-11
Pages: 3
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Systems and Methods for Calculating Common Clock Path Pessimism for Hierarchical Timing Analysis in an Electronic Design
Patent:
10,467,365 →
Application:
15/483,307 →