Patent Assignment
Reel/Frame 042603/0356
Assignment of Assignor's Interest
Recorded: 2017-06-05
Pages: 7
Assignors
GUNARATNA, SENANI
Executed: 2017-06-01
SHARPE-GEISLER, BRAD
Executed: 2017-06-01
YEW, TING
Executed: 2017-06-01
CLINE, RONALD L.
Executed: 2017-06-05
Assignee
LATTICE SEMICONDUCTOR CORPORATION
111 SW 5TH AVENUE, 7TH FLOOR, PORTLAND, OREGON, 97204
Covered Property
(1)
Selective Power Gating of Routing Resource Configuration Memory Bits for Programmable Logic Devices
Patent:
10,079,054 →
Application:
15/614,419 →
Related Assignments
(1)
Other recorded transfers of the patent in this record — the chain of ownership.