Patent Assignment
Reel/Frame 049980/0786
Security Interest
Recorded: 2019-05-21
Pages: 75
Assignor
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2019-05-17
Assignee
WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
1700 LINCOLN STREET, 3RD FLOOR, MAC C7300-033, DENVER, COLORADO, 80203-4500
Covered Properties
(766)
Offset Voltage Calibration Dac with Reduced Sensitivity to Mismatch Errors
Patent:
6,556,154 →
Application:
09/053,251 →
Current-Controlled High Voltage Discharge Scheme
Patent:
6,552,595 →
Application:
09/318,570 →
Enhanced Macrocell Module for High Density Cpld Architectures
Patent:
6,150,841 →
Application:
09/326,140 →
Scalable Architecture for High Density Cpld's Having Two-Level Hierarachy of Routing Resources
Patent:
6,184,713 →
Application:
09/326,940 →
Zero-Power Cmos Non Volatile Memory Cell Having an Avalanche Injection Element
Patent:
6,028,789 →
Application:
09/334,051 →
Non-Volatile Memory Cell Having Dual Avalanche Injection Elements
Patent:
6,034,893 →
Application:
09/334,052 →
Method and Apparatus for Reducing on-Chip Memory in Vertical Video Processing
Patent:
6,587,158 →
Application:
09/359,530 →
Method and Apparatus for Efficient Video Scaling
Patent:
6,681,059 →
Application:
09/363,312 →
Method and Apparatus for Deinterlacing Digital Video Images
Patent:
6,489,998 →
Application:
09/372,713 →
Method and Apparatus for Detecting and Smoothing Diagonal Features Video Images
Patent:
6,515,706 →
Application:
09/396,993 →
Integrated Circuit with Standard Cell Logic and Spare Gates
Patent:
6,404,226 →
Application:
09/400,029 →
On-Line Testing of the Programmable Logic Blocks in Field Programmable Gate Arrays
Patent:
6,550,030 →
Application:
09/405,958 →
On-Line Testing of the Programmable Interconnect Network in Field Programmable Gate Arrays
Patent:
6,574,761 →
Application:
09/406,219 →
Method and Apparatus for Detecting the Source Format of Video Images
Method of Operating Eeprom Memory Cells Having Transistors with Thin Gate Oxide and Reduced Disturb
Patent:
6,208,559 →
Application:
09/441,220 →
Method for in-System Programming of Serially Configured Eeproms Using a Jtag Interface of a Field Programmable Gate Array
Patent:
6,137,738 →
Application:
09/452,017 →
Audio Signal Delay Apparatus and Method
Patent:
7,203,557 →
Application:
09/478,122 →
Integrated Programmable Continuous Time Filter with Programmable Capacitor Arrays
Patent:
6,424,209 →
Application:
09/507,580 →
Decoded generic routing pool
Patent:
6,288,937 →
Application:
09/567,898 →
On-Line Fault Tolerant Operation via Incremental Reconfiguration of Field Programmable Gate Arrays
Patent:
6,530,049 →
Application:
09/611,449 →
Compact Single-Poly Two-Transistor Eeprom Cell
Patent:
6,627,947 →
Application:
09/643,279 →
High Speed Schmitt Trigger with Low Supply Voltage
Patent:
6,433,602 →
Application:
09/651,689 →
High voltage CMOS switch
Patent:
6,370,071 →
Application:
09/660,707 →
Double Differential Comparator and Programmable Analog Block Architecture Using Same
Patent:
6,701,340 →
Application:
09/668,896 →
On-Line Testing of Field Programmable Gate Array Resources
Patent:
6,631,487 →
Application:
09/671,853 →
Cyclic phase signal generation from a single clock source using current phase interpolation
Patent:
6,380,783 →
Application:
09/688,536 →
Wide Input Programmable Logic System and Method
Patent:
6,507,212 →
Application:
09/704,487 →
Scalable architecture for high density cPLD's having two-level hierarchy of routing resources
Patent:
6,348,813 →
Application:
09/721,153 →
Combination of Bpteos Oxide Film with Cmp and Rta to Achieve Good Data Retention
Programmable Power Management System and Method
Voltage Level Translator Systems and Methods
Sense Amplifier Systems and Methods
Patent:
6,414,521 →
Application:
09/775,489 →
Programming Programmable Logic Devices Using Hidden Switches
Method, System and Article of Manufacture for Identifying the Source Type and Quality Level of a Video Sequence
Fully Differential Continuous-Time Current-Mode High Speed Cmos Comparator
Clock Signal Selection System, Method of Generating a Clock Signal and Programmable Clock Manager Including Same
Signal Distribution Scheme in Field Programmable Gate Array (Fpga) or Field Programmable System Chip (Fpsc) Including Cycle Stealing Units
Multi-Master Multi-Slave System Bus in a Field Programmable Gate Array (Fpga)
Double Data Rate Input and Output in a Programmable Logic Device
Multi-Functional I/O Buffers in a Field Programmable Gate Array (Fpga)
Field Programmable Gate Array (Fpga) Bit Stream Format
Low Jitter Integrated Phase Locked Loop with Broad Tuning Range
Patent:
6,498,538 →
Application:
09/870,877 →
Low Voltage, High Speed Cmos Cml Latch and Mux Devices
Patent:
6,614,291 →
Application:
09/881,950 →
High Speed Data Sampling with Reduced Metastability
Patent:
6,429,692 →
Application:
09/885,243 →
Method of Testing Serial Interface
Patent:
6,625,560 →
Application:
09/904,783 →
Clock Jitter Limiting Scheme in Video Transmission Through Multiple Stages
Patent:
7,123,307 →
Application:
09/905,318 →
Method and Apparatus for Adaptive Control of Pll Loop Bandwidth
Patent:
7,062,004 →
Application:
09/905,511 →
System and Method for Measuring Pseudo Pixel Error Rate
Patent:
6,944,804 →
Application:
09/905,615 →
Coupling for Lc-Based Vco
Patent:
6,492,877 →
Application:
09/927,289 →
Enhanced Macrocell Module Having Expandable Product Term Sharing Capability for Use in High Density Cpld Architectures
Low Voltage Bandgap Reference Circuit
Patent:
6,489,835 →
Application:
09/941,454 →
Interlace Motion Artifact Detection Using Vertical Frequency Detection and Analysis
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
Patent:
7,131,004 →
Application:
09/945,278 →
Differential Amplifiers Using Asymmetric Transfer Characteristics to Suppress Input Noise in Output Logic Signals
Patent:
6,985,005 →
Application:
09/989,487 →
High-Speed Bus with Embedded Clock Signals
Patent:
6,845,461 →
Application:
09/989,590 →
System and Method for Multiple-Phase Clock Generation
Patent:
6,809,567 →
Application:
09/989,645 →
Logic Gates Including Diode-Connected Metal-Oxide-Semiconductor Field-Effect Transistors (Mosfets) to Control Input Threshold Voltage Levels and Switching Transients of Output Logic Signals
Patent:
7,058,121 →
Application:
09/989,647 →
Method and System for Encrypting and Decrypting Data Using an External Agent
Patent:
7,242,766 →
Application:
09/991,057 →
Zero-Power Programmable Memory Cell
Patent:
6,611,463 →
Application:
09/991,245 →
Zero-Power Logic Cell for Use in Programmable Logic Devices
Patent:
6,489,806 →
Application:
09/992,493 →
Digital Phase Locked Loop with Programmable Digital Filter
Patent:
6,993,108 →
Application:
10/006,516 →
Digital Phase Locked Loop with Phase Selector Having Minimized Number of Phase Interpolators
Patent:
7,003,066 →
Application:
10/006,559 →
Clock Data Recovery Deserializer with Programmable Sync Detect Logic
Patent:
6,999,543 →
Application:
10/006,610 →
Single-Poly Two-Transistor Eeprom Cell with Differentially Doped Floating Gate
Patent:
6,693,830 →
Application:
10/011,549 →
Method and System for Spatial-Temporal Dithering for Displays with Overlapping Pixels
Patent:
6,714,206 →
Application:
10/016,247 →
Programmable Input/Output Cell with Bidirectional and Shift Register Capabilities
Patent:
6,674,303 →
Application:
10/017,725 →
Structure and Method for Implementing Wide Multiplexers
Patent:
6,605,959 →
Application:
10/017,859 →
I/O Block for a Programmable Interconnect Circuit
Patent:
6,703,860 →
Application:
10/021,844 →
Programmable Interconnect Circuit with a Phase-Locked Loop
Patent:
6,661,254 →
Application:
10/021,873 →
Block-Oriented Architecture for a Programmable Interconnect Circuit
Patent:
7,154,298 →
Application:
10/022,464 →
Multi-Level Routing Structure for a Programmable Interconnect Circuit
Patent:
6,653,861 →
Application:
10/023,053 →
High Speed Interface for a Programmable Interconnect Circuit
Method and System for Host Handling of Communications Errors
Memory Architecture with Multiple Serial Communications Ports
Method and System for Transition-Controlled Selective Block Inversion Communications
Method and System for Dc-Balancing at the Physical Layer
Patent:
6,771,192 →
Application:
10/045,600 →
Multisection Memory Bank System
Method and System for Integrating Packet Type Information with Synchronization Symbols
Supporting Circuitry and Method for Controlling Pixels
Patent:
7,109,958 →
Application:
10/047,772 →
Test structure for determining a minimum tunnel opening size in a non-volatile memory
Method and System for Communicating Control Information via Out-of-Band Symbols
Deinterlacing of Video Sources via Image Feature Edge Detection
Patent:
7,023,487 →
Application:
10/057,823 →
Integrated Circuit Base Transistor Structure and Associated Programmable Cell Library
Method and System for Temporary Interruption of Video Data Transmission
Patent:
7,035,290 →
Application:
10/085,177 →
Differential Input Comparator
Patent:
6,639,431 →
Application:
10/112,370 →
Zero Power Memory Cell with Improved Data Retention
Patent:
6,660,579 →
Application:
10/128,943 →
Polynomial Expander for Generating Coefficients of a Polynomial from Roots of the Polynomial
Patent:
7,032,162 →
Application:
10/131,883 →
Device and Method with Generic Logic Blocks
Cryptosystems Using Commuting Pairs in a Monoid
Patent:
7,136,484 →
Application:
10/133,813 →
Integrated Circuit and Associated Design Method Using Spare Gate Islands
Band Gap Reference Circuit
Patent:
6,720,755 →
Application:
10/146,734 →
Input Buffer with Selectable Pcl, Gtl, or Pecl Compatibility
Patent:
6,714,048 →
Application:
10/146,739 →
Input Buffer with Cmos Driver Gate Current Control Enabling Selectable Pcl, Gtl, or Pecl Compatibility
Patent:
6,870,391 →
Application:
10/146,769 →
Electrostatic Discharge Protection Circuit
Patent:
6,760,209 →
Application:
10/147,011 →
Output Buffer Having Programmable Drive Current and Output Voltage Limits
Patent:
6,714,043 →
Application:
10/147,199 →
Method of Assigning Logic Functions to Macrocells in a Programmable Logic Device
Patent:
6,848,095 →
Application:
10/150,410 →
Highly Linear Programmable Transconductor with Large Input-Signal Range
Patent:
6,583,652 →
Application:
10/159,009 →
Precision Analog Level Shifter with Programmable Options
Patent:
6,717,451 →
Application:
10/159,089 →
Multimode Output Stage Converting Differential to Single-Ended Signals Using Current-Mode Input Signals
Patent:
6,806,771 →
Application:
10/159,681 →
Determining and Configuring a Communication Path in a Network
Eeprom Device Having a Retrograde Program Junction Region and Process for Fabricating the Device
Patent:
6,716,705 →
Application:
10/161,283 →
Method and Apparatus for Connecting Serial Ata Storage Components
Patent:
6,843,674 →
Application:
10/162,046 →
Converting Bits to Vectors in a Programmable Logic Device
Method and Apparatus for Detecting and Smoothing Diagonal Features in Video Images
Field Programmable Gate Array Based Upon Transistor Gate Oxide Breakdown
Patent:
6,650,143 →
Application:
10/191,888 →
Fpga with Register-Intensive Architecture
Patent:
7,028,281 →
Application:
10/194,771 →
Integrated Programmable Continuous Time Filter with Programmable Capacitor Arrays
Crc Calculation System and Method for a Packet Arriving on an N-Byte Wide Bus
Method and System for Arbitrating Priority Bids Sent Over Serial Links to a Multi-Port Storage Device
Patent:
7,171,525 →
Application:
10/210,839 →
Dynamically Biased Full-Swing Operation Amplifier for an Active Matrix Liquid Crystal Display Driver
Patent:
6,717,468 →
Application:
10/215,936 →
Enhanced Cpld Macrocell Module Having Selectable Bypass of Steering-Based Resource Allocation and Methods of Use
Patent:
6,650,142 →
Application:
10/219,046 →
System and Method for an Adaptive State Machine to Control Signal Filtering in a Serial Link
Patent:
7,218,737 →
Application:
10/224,995 →
Performing Conditional Operations in a Programmable Logic Device
Patent:
7,043,511 →
Application:
10/233,021 →
Scalable and Parallel Processing Methods and Structures for Testing Configurable Interconnect Network in Fpga Device
Patent:
6,725,442 →
Application:
10/235,380 →
Device Having Electically Isolated Low Voltage and High Voltage Regions and Process for Fabricating the Device
Patent:
6,833,602 →
Application:
10/236,114 →
Eeprom Device Having Improved Data Retention and Process for Fabricating the Device
Patent:
6,649,514 →
Application:
10/236,718 →
Sram Cell with Single-Ended and Differential Read/Write Ports
Memory Access Circuit and Method for Reading and Writing Data with the Same Clock Signal
Patent:
6,917,536 →
Application:
10/243,014 →
Through-Board Pcb Edge Connector, System and Method
Patent:
6,814,583 →
Application:
10/244,152 →
Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer
Patent:
8,064,508 →
Application:
10/247,675 →
Method and Apparatus for Deinterlacing Digital Video Images
Method of Routing in a Programmable Logic Device
Patent:
6,907,592 →
Application:
10/255,474 →
State Machine in a Programmable Logic Device
Patent:
6,803,787 →
Application:
10/255,499 →
Vector Routing in a Programmable Logic Device
Patent:
6,812,738 →
Application:
10/255,656 →
Method of Optimizing Routing in a Programmable Logic Device
Patent:
6,809,551 →
Application:
10/255,875 →
Programming Programmable Logic Devices Using Hidden Switches
Patent:
6,748,575 →
Application:
10/263,251 →
Low Voltage Differential Signaling Systems and Methods
Patent:
6,639,434 →
Application:
10/266,361 →
Cryptographic Device with Stored Key Data and Method for Using Stored Key Data to Perform an Authentication Exchange or Self Test
Patent:
7,412,053 →
Application:
10/268,832 →
Verify Scheme for a Multi-Level Routing Structure
Patent:
6,762,618 →
Application:
10/269,439 →
Power Supply Control Circuits
Expansion Method for Complex Power-Sequencing Applications
Patent:
7,111,183 →
Application:
10/269,804 →
Voltage Swing Detection Circuit for Hot Plug Event or Device Detection via a Differential Link
Patent:
7,009,827 →
Application:
10/270,882 →
Power Sequence Controller Programming Technique
Patent:
6,901,572 →
Application:
10/272,582 →
Asynchronous Glitch-Free Clock Multiplexer
Patent:
6,639,449 →
Application:
10/278,415 →
Turbo Encoder with Reduced Processing Delay
Patent:
7,051,261 →
Application:
10/282,524 →
Programmable Common Mode Termination for Input/Output Circuits
Patent:
6,700,823 →
Application:
10/283,765 →
Detection of Video Windows and Graphics Windows
Patent:
6,873,341 →
Application:
10/287,976 →
Adaptive Adjustment of Constraints During Pld Placement Processing
Placement Processing for Programmable Logic Devices
Integrated Circuit Having Self Test Capability Using Message Digest and Method for Testing Integrated Circuit Having Message Digest Generation Circuitry
Patent:
7,539,304 →
Application:
10/298,722 →
Low Jitter Integrated Phase Locked Loop with Broad Tuning Range
Patent:
6,825,733 →
Application:
10/300,190 →
Age Selection Switching Scheme for Data Traffic in a Crossbar Switch
Patent:
7,274,690 →
Application:
10/302,436 →
Flash Technology Transistors and Methods for Forming the Same
Patent:
6,797,568 →
Application:
10/302,439 →
Bandgap Reference Circuit for Improved Start-Up
Patent:
6,710,641 →
Application:
10/308,420 →
Coupling for Lc-Based Vco
Patent:
6,650,188 →
Application:
10/309,302 →
Fifo Memory Architecture
Patent:
6,777,979 →
Application:
10/334,642 →
Adaptive Input Logic for Phase Adjustments
Programmable Interface Circuit for Differential and Single-Ended Signals
Noise Reduction Techniques for Programmable Input/Output Circuits
Patent:
6,812,869 →
Application:
10/367,323 →
Macrocells Supporting a Carry Cascade
Patent:
6,915,323 →
Application:
10/368,023 →
Dynamic Cross Point Switch with Shadow Memory Architecture
Patent:
6,861,870 →
Application:
10/370,232 →
Bank-Based Input/Output Buffers with Multiple Reference Voltages
Patent:
6,859,066 →
Application:
10/377,320 →
Pointer Processing for Optical Communication Systems
Patent:
7,339,952 →
Application:
10/387,243 →
Automatic Lane Assignment for a Receiver
Patent:
7,305,047 →
Application:
10/387,814 →
Programmable Logic Devices with Integrated Standard-Cell Logic Blocks
Electronic Circuit with on-Chip Programmable Terminations
Patent:
6,967,500 →
Application:
10/397,669 →
Method and Apparatus for Controlling Signal Distribution in an Electronic Circuit
Patent:
6,873,187 →
Application:
10/400,705 →
Continuous-Time, Low-Frequency-Gain/High-Frequency-Boosting Joint Adaptation Equalizer and Method
Patent:
6,819,166 →
Application:
10/403,477 →
Hierarchical General Interconnect Architecture for High Density Fpga's
Fifo Memory with Programmable Data Port Widths
Patent:
6,986,004 →
Application:
10/409,543 →
Programmable Logic Device Architecture Based on Arrays of Lut-Based Boolean Terms
Patent:
6,879,184 →
Application:
10/417,290 →
Video/Graphics Text Mode Enhancement Method for Digitally Processed Data
Patent:
7,348,991 →
Application:
10/417,712 →
Programmable and Fixed Logic Circuitry for High-Speed Interfaces
Patent:
6,894,530 →
Application:
10/425,862 →
Scalable Device Architecture for High-Speed Interfaces
Patent:
6,903,575 →
Application:
10/425,863 →
Cascaded Logic Block Architecture for Complex Programmable Logic Devices
Patent:
6,861,871 →
Application:
10/428,885 →
Multi-Stage Interconnect Architecture for Complex Programmable Logic Devices
Patent:
6,864,713 →
Application:
10/428,888 →
Cpld with Multi-Function Blocks and Distributed Memory
Patent:
6,879,182 →
Application:
10/428,889 →
Programmable Logic Device with Enhanced Wide and Deep Logic Capability
Patent:
6,922,078 →
Application:
10/428,982 →
Method for Switching Data in a Crossbar Switch
Patent:
7,519,066 →
Application:
10/434,785 →
Method and Circuit for Dc Measurement of Phase Uniformity of Multi-Phase Clocks
Patent:
7,031,858 →
Application:
10/439,446 →
Non-Volatile and Reconfigurable Programmable Logic Devices
Patent:
6,828,823 →
Application:
10/439,602 →
Measuring Propagation Delays of Programmable Logic Devices
Patent:
7,039,842 →
Application:
10/441,814 →
Skew Cancellation for Source Synchronous Clock and Data Signals
Patent:
7,301,996 →
Application:
10/447,120 →
Digitally Controlled Delay Cells
Integrated Circuit Including External Electronic Components with Low Insertion Loss
Patent:
7,304,863 →
Application:
10/457,630 →
Flexible Media Access Control Architecture
Method and Apparatus for Encoding or Decoding Data in Accordance with an Nb/(N+1)B Block Code, and Method for Determining Such a Block Code
Patent:
6,747,580 →
Application:
10/459,992 →
Synchronization of Programmable Multiplexers and Demultiplexers
Patent:
6,856,171 →
Application:
10/460,385 →
High Speed Interface for a Programmable Interconnect Circuit
Patent:
6,861,868 →
Application:
10/463,781 →
Bi-Directional Buffering for Memory Data Lines
Integrated Circuit and Associated Design Method Using Spare Gate Islands
Patent:
6,822,477 →
Application:
10/600,042 →
Noise-Shielding, Switch-Controlled Load Circuitry for Oscillators and the Like
Patent:
7,132,903 →
Application:
10/613,460 →
Programmable I/O Interfaces for Fpgas and Other Plds
Patent:
6,952,115 →
Application:
10/613,462 →
Programmable Logic Device with Hardwired Microsequencer
Patent:
6,958,625 →
Application:
10/617,980 →
Scalable Serializer-Deserializer Architecture and Programmable Interface
Patent:
7,098,685 →
Application:
10/619,645 →
Programmable Logic Device with Enhanced Wide Input Product Term Cascading
Patent:
6,903,573 →
Application:
10/619,711 →
Algorithm to Increase Logic Input Width by Cascading Product Terms
Patent:
7,032,203 →
Application:
10/620,147 →
Field Programmable Gate Array Having Embedded Memory with Configurable Depth and Width
Patent:
6,919,736 →
Application:
10/620,286 →
Programmable Logic Device with a Memory-Based Finite State Machine
Patent:
6,940,309 →
Application:
10/624,965 →
Programmable Lock Detector and Corrector
Patent:
6,970,047 →
Application:
10/628,656 →
Programmable Signal Termination for Fpgas and the Like
Patent:
6,924,659 →
Application:
10/628,657 →
Clock Generator with Skew Control
Clock Generator
Memory Access via Serial Memory Interface
Integrated Circuit and Associated Design Method with Antenna Error Control Using Spare Gates
Patent:
6,877,667 →
Application:
10/640,804 →
Enhanced Cpld Macrocell Module Having Selectable Bypass of Steering-Based Resource Allocation
Patent:
6,838,904 →
Application:
10/640,828 →
Programmable Broadcast Initialization of Memory Blocks
Field Programmable Gate Array
Preference Programmable First-One Detector and Quadrature Based Random Grant Generator
Patent:
7,505,422 →
Application:
10/645,786 →
Method for Multicast Service in a Crossbar Switch
Patent:
7,461,167 →
Application:
10/645,787 →
Shared Transmission Line Communication System and Method
Patent:
6,842,037 →
Application:
10/655,686 →
Delay-Matched Asic Conversion of a Programmable Logic Device
Patent:
7,038,490 →
Application:
10/660,814 →
Detection and Repair of Mpeg-2 Chroma Upconversion Artifacts
Controlled Hysteresis Comparator with Rail-to-Rail Input
Patent:
6,970,022 →
Application:
10/665,920 →
Programmable I/O Structure for Fpgas and the Like Having Shared Circuitry
Patent:
6,943,582 →
Application:
10/671,363 →
Programmable I/O Structure for Fpgas and the Like Having Reduced Pad Capacitance
Patent:
6,943,583 →
Application:
10/671,378 →
Multiport Memory with Twisted Bitlines
Patent:
6,909,663 →
Application:
10/671,756 →
Semiconductor Device Adapted for Forming Multiple Scan Chains
Patent:
7,269,771 →
Application:
10/676,536 →
Analog-To-Digital Converters
Patent:
6,809,674 →
Application:
10/687,468 →
Lateral High-Voltage Junction Device
Clock Generation
Patent:
7,091,763 →
Application:
10/701,005 →
Programmable Logic Device with Flexible Memory Allocation and Routing
Patent:
7,088,134 →
Application:
10/704,025 →
Programmable Power Management System and Method
Patent:
7,100,058 →
Application:
10/726,972 →
Linear Thermoelectric Device Driver
Patent:
6,981,381 →
Application:
10/737,514 →
Method for Configuring Multiple-Output Phase-Locked Loop Frequency Synthesizer
Patent:
7,132,864 →
Application:
10/744,353 →
Video Stream Routing and Format Conversion Unit with Audio Delay
Patent:
7,400,359 →
Application:
10/753,909 →
Content Addressable Merged Queue Architecture for Switching Data
Patent:
7,352,764 →
Application:
10/762,950 →
Reduced Dead-Cycle, Adaptive Phase Tracking Method and Apparatus
Patent:
7,236,553 →
Application:
10/763,905 →
Output Stages for High Current Low Noise Bandgap Reference Circuit Implementations
Electrostatic Discharge Simulation
Combination Field Programmable Gate Array Allowing Dynamic Reprogrammability and Non-Volatile Programmability Based Upon Transistor Gate Oxide Breakdown
Upgradeable and Reconfigurable Programmable Logic Device
Semiconductor Memory Device
Fast Diagonal Interleaved Parity (Dip) Calculator
Patent:
7,191,388 →
Application:
10/791,073 →
Method and Circuit for Adaptive Equalization of Multiple Signals in Response to a Control Signal Generated from One of the Equalized Signals
Timer Systems and Methods
Powering-Up a Device Having Digital and Analog Circuitry
Systems and Methods for Controlling Voltage Regulator Module Power Supplies
Sense Amplifier Systems and Methods
Table-Based Scheduler for Fifos and the Like
Patent:
7,234,030 →
Application:
10/809,180 →
Configuring Fpgas and the Like Using One or More Serial Memory Devices
Patent:
7,095,247 →
Application:
10/809,658 →
Self-Adjusting Schmitt Trigger
Patent:
7,167,032 →
Application:
10/815,403 →
Charge Pump for a Low-Voltage Wide-Tuning Range Phase-Locked Loop
Dynamic Gain Adjustment Systems and Methods for Metastability Resistance
Patent:
6,998,896 →
Application:
10/829,865 →
Low Pass Filter Systems and Methods
Patent:
6,998,906 →
Application:
10/834,528 →
Method and Apparatus for Run Length Limited Tmds-Like Encoding of Data
Patent:
6,897,793 →
Application:
10/835,301 →
High-Voltage Protection Device and Process
Patent:
7,307,319 →
Application:
10/837,086 →
Switched Capacitor Ripple-Smoothing Filter
Data Sampling Method and Apparatus Using Through-Transition Counts to Reject Worst Sampling Position
Patent:
7,991,096 →
Application:
10/842,231 →
Control Signal Generation for a Low Jitter Switched-Capacitor Frequency Synthesizer
I/O Buffer Architecture for Programmable Devices
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7,061,269 →
Application:
10/843,708 →
Current Mode Logic Buffer
Combination Field Programmable Gate Array Allowing Dynamic Reprogrammability
Memory Systems and Methods
Time Base Correction and Frame Rate Conversion
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10/889,855 →
Byte Enable Logic for Memory
Data Transmission Synchronization
Process for Fabricating a Semiconductor Device Having Electrically Isolated Low Voltage and High Voltage Regions
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10/928,563 →
Testing Embedded Memory in an Integrated Circuit
Field Programmable Gate Arrays Using Both Volatile and Nonvolatile Memory Cell Properties and Their Control
Memory Output Data Systems and Methods with Feedback
Field Programmable Gate Array Logic Unit and Its Cluster
Variable Data Width Memory Systems and Methods
Patent:
7,307,912 →
Application:
10/974,453 →
Testing Embedded Memory in Integrated Circuits Such as Programmable Logic Circuit
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7,376,872 →
Application:
10/978,899 →
Low Power Asynchronous Sense Amp
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7,161,862 →
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10/996,283 →
Dynamic Over-Voltage Protection Scheme for Integrated-Circuit Devices
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7,230,810 →
Application:
11/007,954 →
Programmable Current Output Buffer
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7,215,148 →
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11/012,548 →
Interface Circuitry for Electrical Systems
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11/012,550 →
Initializing Memory Blocks
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11/015,265 →
Sense Amplifier Timing
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11/015,369 →
Cascadable Memory
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7,187,203 →
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11/016,665 →
Self-Verification of Configuration Memory in Programmable Logic Devices
Patent:
7,257,750 →
Application:
11/036,630 →
Eeprom Device with Voltage-Limiting Charge Pump Circuit
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11/036,738 →
Serdes with Programmable I/O Architecture
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Application:
11/040,772 →
Synchronous Memory
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7,183,798 →
Application:
11/041,319 →
Synchronization of Programmable Multiplexers and Demultiplexers
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7,109,754 →
Application:
11/044,089 →
Synchronization of Programmable Multiplexers and Demultiplexers
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7,109,756 →
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11/044,149 →
Clock Generator with Skew Control
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7,034,599 →
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11/044,508 →
Multi-Port Memory Systems and Methods for Bit Line Coupling
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7,221,607 →
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11/054,011 →
Interlace Motion Artifact Detection Using Vertical Frequency Detection and Analysis
Data Decompression
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7,382,293 →
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11/054,750 →
Data Decompression
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7,589,648 →
Application:
11/054,855 →
Programmable Logic Devices with Integrated Standard-Cell Logic Blocks
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6,975,137 →
Application:
11/055,280 →
Phase Lock Loop with Coarse Control Loop Having Frequency Lock Detector and Device Including Same
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7,102,446 →
Application:
11/056,995 →
Distributed Multiple-Channel Alignment Scheme
Output Impedance Measurement Techniques
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7,057,397 →
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11/070,926 →
Differential Input Receiver with Programmable Failsafe
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Application:
11/071,356 →
Detection of Unknown Symbol Rate in a Digitally Modulated Signal
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7,376,204 →
Application:
11/083,625 →
In-System Programming of Non-Jtag Device Using Spi and Jtag Interfaces of Fpga Device
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7,265,578 →
Application:
11/098,713 →
In-System Programming of a Non-Compliant Device Using Multiple Interfaces of a Pld
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7,397,274 →
Application:
11/100,718 →
Fast Processing Path Using Field Programmable Gate Array Logic Unit
Analog-To-Digital Systems and Methods
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7,630,464 →
Application:
11/109,301 →
Field Programmable Gate Array
Electronic Switch Having Extended Voltage Range
Patent:
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11/121,326 →
Programmable I/O Interfaces for Fpgas and Other Plds
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7,009,423 →
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11/134,152 →
Design Features for Testing Integrated Circuits
Patent:
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Decoding Systems and Methods
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7,378,879 →
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Programmable Interconnect Architecture for Programmable Logic Devices
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Application:
11/165,709 →
Programmable Logic Device with a Double Data Rate Sdram Interface
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Application:
11/165,853 →
Signal Monitoring Systems and Methods
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7,519,139 →
Application:
11/185,242 →
Output Clock Phase-Alignment Circuit
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Application:
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Address Decoding Systems and Methods
Receiver for Differential and Reference-Voltage Signaling with Programmable Common Mode
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7,505,752 →
Application:
11/189,067 →
Programmable Termination for Single-Ended and Differential Schemes
Patent:
7,262,630 →
Application:
11/194,356 →
Bitline Twisting Scheme for Multiport Memory
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7,414,913 →
Application:
11/194,871 →
Clock-And-Data-Recovery System Having a Multi-Phase Clock Generator for One or More Channel Circuits
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7,411,419 →
Application:
11/200,941 →
Programmable Logic Device with Enhanced Logic Block Architecture
Patent:
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Application:
11/200,983 →
Flash Memory Erase Verification Systems and Methods
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7,187,586 →
Application:
11/201,620 →
Correlator Having User-Defined Processing
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7,301,182 →
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Data Transfer Verification Systems and Methods
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7,167,405 →
Application:
11/230,087 →
Programmable Logic Device with Power-Saving Architecture
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7,376,037 →
Application:
11/235,616 →
Electrostatic Protection Systems and Methods
Configuring Fpgas and the Like Using One or More Serial Memory Devices
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7,088,132 →
Application:
11/243,255 →
Address Isolation for User-Defined Configuration Memory in Programmable Devices
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7,196,963 →
Application:
11/251,682 →
Clock Reset Address Decoder for Block Memory
Field Programmable Gate Array
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7,685,215 →
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11/257,137 →
Pulse-Generation Circuit with Multi-Delay Block and Set-Reset Latches
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11/257,641 →
Control Signal Generation for a Low Jitter Switched-Capacitor Frequency Synthesizer
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11/260,097 →
Digital I/O Timing Control
Interface Block Architectures
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7,327,159 →
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11/287,720 →
Pseudo-Dynamic Word-Line Driver
Transparent Field Reconfiguration for Programmable Logic Devices
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7,538,574 →
Application:
11/293,941 →
Temperature-Independent, Linear on-Chip Termination Resistance
Jitter Tolerant Delay-Locked Loop Circuit
Covert Channel for Conveying Supplemental Messages in a Protocol-Defined Link for a System of Storage Devices
Differential Amplifiers Using Asymmetric Transfer Characteristics to Suppress Input Noise in Output Logic Signals
Systems and Methods for Reducing Static Phase Error
Phase-Locked Loop Systems and Methods
Dynamic Over-Voltage Protection Scheme for Interface Circuitry
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7,547,995 →
Application:
11/345,713 →
Efficient Configuration of Daisy-Chained Programmable Logic Devices
Reconfiguration of Programmable Logic Devices
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Application:
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Memory Cell Comprising an Otp Nonvolatile Memory Unit and a Sram Unit
Method and Apparatus for Detecting Frequency in Digital Video Images
Programmable Logic Devices with Distributed Memory and Non-Volatile Memory
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7,355,441 →
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11/360,337 →
Auto Recovery from Volatile Soft Error Upsets (Seus)
Patent:
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11/361,584 →
Comparator Systems and Methods
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7,446,573 →
Application:
11/361,643 →
Dynamic Phase Offset Measurement
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Programmable Logic Devices with User Non-Volatile Memory
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7,554,358 →
Application:
11/397,985 →
Programmable Logic Devices with Transparent Field Reconfiguration
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7,459,931 →
Application:
11/398,437 →
Programmable Logic Function Generator Using Non-Volatile Programmable Memory Switches
Selective Programming of Non-Volatile Memory Facilitated by Security Fuses
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7,623,378 →
Application:
11/416,881 →
Key Generation for Advanced Encryption Standard (Aes) Decryption and the Like
Clock Distribution Chip for Generating Both Zero-Delay and Non-Zero-Delay Clock Signals
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7,657,773 →
Application:
11/425,881 →
Sense Amplifier Systems and Methods
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Application:
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Programmable Logic Device Architecture with Multiple Slice Types
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Application:
11/445,620 →
Programmable Logic Devices with Custom Identification Systems and Methods
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Flexible Memory Architectures for Programmable Logic Devices
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Logic Block Control Architectures for Programmable Logic Devices
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Dual Slice Architectures for Programmable Logic Devices
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Application:
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Programmable Logic Device Providing a Serial Peripheral Interface
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7,378,873 →
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11/446,548 →
Programmable Logic Device Methods and System for Providing Multi-Boot Configuration Data Support
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7,631,223 →
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Programmable Logic Device and Method of Testing
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Application:
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Upgradeable and Reconfigurable Programmable Logic Device
Integrated Circuits and Complementary Cmos Circuits for Frequency Dividers
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7,411,432 →
Application:
11/461,222 →
Method and Systems to Align Output Signals of an Analog-to-Digital Converter
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7,348,914 →
Application:
11/477,759 →
Original Scan Line Detection
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Application:
11/487,647 →
Negative Voltage Blocking for Embedded Memories
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7,512,015 →
Application:
11/487,751 →
Charge Pump with Four-Well Transistors
Switch Sequencing Circuit Systems and Methods
Methods and Systems for Storing a Security Key Using Programmable Fuses
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7,675,313 →
Application:
11/498,645 →
Area Efficient Routing Architectures for Programmable Logic Devices
Patent:
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Application:
11/498,646 →
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
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Source-Adaptive Video Deinterlacer
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7,456,672 →
Application:
11/530,620 →
Efficient Bitstream Compression
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Application:
11/533,188 →
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
Multiple Communication Channel Configuration Systems and Methods
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Application:
11/551,459 →
Multiplexer Initialization Systems and Methods
Patent:
7,663,401 →
Application:
11/556,528 →
Programmable Logic Device Programming Verification Systems and Methods
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Application:
11/557,808 →
Method of Context Adaptive Binary Arithmetic Coding and Coding Apparatus Using the Same
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11/567,514 →
Planar Antenna
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Application:
11/588,472 →
Programmable Current Output and Common-Mode Voltage Buffer
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7,535,258 →
Application:
11/593,274 →
Data Transfer Verification Systems and Methods
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Application:
11/624,021 →
Adaptive Bandwidth Phase Locked Loop with Feedforward Divider
Low Static Current Drain Logic Circuit
Output Buffer with Digital Slew Control
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Application:
11/643,288 →
Current Mode Circuitry to Modulate a Common Mode Voltage
Concurrent Code Checker and Hardware Efficient High-Speed I/O Having Built-in Self-Test and Debug Features
Parallel Interface Bus to Communicate Video Data Encoded for Serial Data Links
High Fan-Out Signal Routing Systems and Methods
Patent:
7,576,563 →
Application:
11/671,948 →
Flash Memory Erase Verification Systems and Methods
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Application:
11/675,246 →
Diagonal Interleaved Parity Calculator
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Application:
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Serdes with Programmable I/O Architecture
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7,327,160 →
Application:
11/676,196 →
Redundant Configuration Memory Systems and Methods
Shared Nonvolatile Memory Architecture
Progressive Power Control of a Multi-Port Memory Device
Power-Saving Clocking Technique
Logic Analyzer Systems and Methods for Programmable Logic Devices
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7,536,615 →
Application:
11/691,003 →
Logic Analyzer Systems and Methods for Programmable Logic Devices
Patent:
7,743,296 →
Application:
11/691,040 →
Multi-Port Memory Device Having Variable Port Speeds
Inter-Port Communication in a Multi-Port Memory Device
Clock Boosting Systems and Methods
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Application:
11/737,702 →
Interface Test Circuitry and Methods
Integrated Circuit Temperature Sensor Systems and Methods
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Application:
11/750,616 →
Self-Verification of Configuration Memory in Programmable Logic Devices
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7,401,280 →
Application:
11/750,790 →
Digital Video Interface with Bi-Directional Half-Duplex Clock Channel Used as Auxiliary Data Channel
Soft Error Detection Logic Testing Systems and Methods
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8,065,574 →
Application:
11/760,411 →
Programmable Logic Device Providing Serial Peripheral Interfaces
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7,570,078 →
Application:
11/761,221 →
Distributed Front-End Fifo for Source-Synchronized Interfaces with Non-Continuous Clocks
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7,573,770 →
Application:
11/778,457 →
Compression and Decompression of Configuration Data for Programmable Logic Devices
Patent:
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Application:
11/779,246 →
Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer
On Screen Displays Associated with Remote Video Source Devices
Data Stream Control for Network Devices
Communications Architecture for Transmission of Data Between Memory Bank Caches and Ports
Packet Level Prioritization in Interconnection Networks
Bandwidth Reservation for Data Flows in Interconnection Networks
Network Repository for Metadata
Synchronizing Related Data Streams in Interconnection Networks
Ensuring Physical Locality of Entities Sharing Data
Delivering on Screen Display Data to Existing Display Devices
Signal Interleaving for Serial Clock and Data Recovery
Weight Based Look Up Table Collapsing for Programmable Logic Devices
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Application:
11/863,016 →
Variable Data Width Memory Systems and Methods
Patent:
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Application:
11/865,556 →
Hysteresis-Based Processing for Applications Such as Signal Bias Monitors
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Application:
11/869,019 →
Dynamic Delay or Advance Adjustment of Oscillating Signal Phase
Patent:
7,586,344 →
Application:
11/872,950 →
Scan Chain Systems and Methods for Programmable Logic Devices
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7,757,198 →
Application:
11/875,748 →
Single-Ended Output Driver Buffer
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7,411,414 →
Application:
11/877,434 →
Channel-To-Channel Deskew Systems and Methods
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Application:
11/924,088 →
Interlace Motion Artifact Detection Using Vertical Frequency Detection and Analysis
Programmable Logic Device with Enhanced Logic Block Architecture
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Application:
11/934,711 →
Simultaneous Switching Output Noise Estimation and Reduction Systems and Methods
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7,895,555 →
Application:
11/937,300 →
Input/Output Placement Systems and Methods to Reduce Simultaneous Switching Output Noise
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Application:
11/937,328 →
Flexible Delay Cell Architecture
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Application:
11/939,787 →
Register Data Retention Systems and Methods During Reprogramming of Programmable Logic Devices
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7,535,253 →
Application:
11/941,006 →
Compression and Decompression of Configuration Data Using Repeated Data Frames
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7,902,865 →
Application:
11/941,031 →
Noise Cancellation
Composite Wire Indexing for Programmable Logic Devices
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7,788,623 →
Application:
11/947,662 →
Integrated Circuit Having Independent Voltage and Process/Temperature Control
Patent:
7,586,325 →
Application:
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Interface Block Architectures
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7,427,874 →
Application:
11/949,454 →
Cryptographic Device with Stored Key Data and Method for Using Stored Key Data to Perform an Authentication Exchange or Self Test
Patent:
7,797,536 →
Application:
11/950,088 →
Bank Sharing and Refresh in a Shared Multi-Port Memory Device
Programmable Level Shifter
Patent:
7,605,609 →
Application:
11/957,598 →
Programmable Logic Device with Built in Self Test
Patent:
7,630,259 →
Application:
11/959,329 →
Process Charging Monitor for Nonvolatile Memory
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7,646,643 →
Application:
11/970,212 →
Serial Interface for Programmable Logic Devices
Patent:
7,728,625 →
Application:
12/001,600 →
Programmable Logic Device with a Multi-Data Rate Sdram Interface
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7,787,326 →
Application:
12/019,526 →
Internally Triggered Reconfiguration of Programmable Logic Devices
Patent:
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Application:
12/021,202 →
Reconfiguration of Programmable Logic Devices
Patent:
7,652,500 →
Application:
12/044,842 →
Wire Mapping for Programmable Logic Devices
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7,890,913 →
Application:
12/055,170 →
Bi-Directional Digital Interface for Video and Audio (Diva)
Programmable Logic Devices with Distributed Memory
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7,459,935 →
Application:
12/060,776 →
Detection of Timing Errors in Programmable Logic Devices
Patent:
7,831,856 →
Application:
12/061,885 →
On-Chip Temperature Sensor for an Integrated Circuit
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7,661,878 →
Application:
12/099,933 →
Programmable Logic Device with Power-Saving Architecture
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7,558,143 →
Application:
12/100,859 →
Synchronization of Data Signals and Clock Signals for Programmable Logic Devices
Patent:
7,557,606 →
Application:
12/105,146 →
Programmable Logic Device with Multiple Slice Types
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7,696,784 →
Application:
12/105,959 →
Power Management Systems and Methods for Programmable Logic Devices
Patent:
7,560,953 →
Application:
12/107,883 →
Formation of High Voltage Transistor with High Breakdown Voltage
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7,897,448 →
Application:
12/122,489 →
Digital Signal Processing Block Architecture for Programmable Logic Device
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8,463,832 →
Application:
12/146,042 →
Logic Block Control Architectures for Programmable Logic Devices
Patent:
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Application:
12/164,265 →
Methods and Mechanisms for Probabilistic Color Correction
Synchronization of Serial Data Signals
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Application:
12/182,940 →
Selective Loading of Configuration Data into Configuration Memory Cells
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7,579,865 →
Application:
12/186,027 →
Low-Power Output Driver Buffer Circuit
Patent:
7,605,602 →
Application:
12/188,120 →
Group Power Management of Network Devices
System, Method, and Apparatus for Smoothing of Edges in Images to Remove Irregularities
Programmable Signal Routing Systems Having Low Static Leakage
Coding System for Memory Systems Employing High-Speed Serial Links
Clock Systems and Methods
Patent:
7,663,419 →
Application:
12/273,868 →
Transmitter and Receiver Using Asymmetric Transfer Characteristics in Differential Amplifiers to Suppress Noise
Congestion-Driven Placement Systems and Methods for Programmable Logic Devices
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8,112,731 →
Application:
12/277,217 →
Method, Apparatus and System for Employing a Content Protection System
Congestion Estimation for Programmable Logic Devices
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7,992,120 →
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12/323,974 →
Programmable Logic Device and Method of Testing
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7,656,193 →
Application:
12/327,128 →
Congestion Estimation Based on Routing Resources of Programmable Logic Devices
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8,856,718 →
Application:
12/337,502 →
Multi-Priority Placement for Configuring Programmable Logic Devices
Patent:
8,181,139 →
Application:
12/341,929 →
Method, Apparatus, and System for Pre-Authentication and Keep-Authentication of Content Protected Ports
Method and System for Detecting Successful Authentication of Multiple Ports in a Time-Based Roving Architecture
Fault Testing for Interconnections
Temperature-Independent, Linear on-Chip Termination Resistance
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7,714,608 →
Application:
12/370,039 →
Flexible Memory Architectures for Programmable Logic Devices
Patent:
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Application:
12/389,149 →
Method, Apparatus, and System for Deciphering Media Content Stream
Method, Apparatus, and System for Pre-Authentication and Processing of Data Streams
Receiver for Differential and Reference Voltage Signaling with Programmable Common Mode
Patent:
7,844,243 →
Application:
12/402,751 →
Routing Signals to Pins of Components in Programmable Logic Devices
Patent:
8,069,431 →
Application:
12/406,772 →
Clock Boosting Systems and Methods
Patent:
8,086,986 →
Application:
12/408,047 →
Dual-Slice Architectures for Programmable Logic Devices
Patent:
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12/409,757 →
Efficient Bitstream Compression
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7,808,405 →
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12/413,787 →
Soft Error Upset Hardened Integrated Circuit Systems and Methods
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7,741,865 →
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12/430,848 →
Register Data Retention Systems and Methods During Reprogramming of Programmable Logic Devices
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7,876,125 →
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12/464,822 →
Reading an External Memory Device to Determine Its Interface Characteristics for Configuring a Programmable Logic Device
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7,868,654 →
Application:
12/465,444 →
Transparent Field Reconfiguration for Programmable Logic Devices
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Application:
12/467,800 →
Fpga Having Low Power, Fast Carry Chain
Programmable Logic Devices with Custom Identification Systems and Methods
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7,702,977 →
Application:
12/480,565 →
Detection of Encryption Utilizing Error Detection for Received Data
In-System Reconfigurable Circuit for Mapping Data Words of Different Lengths
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8,165,164 →
Application:
12/494,822 →
Power Management for Integrated Circuits Such as Programmable Logic Devices
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7,724,029 →
Application:
12/502,141 →
Programmable Logic Device Providing Serial Peripheral Interfaces
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Application:
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Signaling for Transitions Between Modes of Data Transmission
Clock Delay and Skew Control Systems and Methods
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8,255,733 →
Application:
12/512,944 →
Oscillator Tuning for Phase-Locked Loop Circuit
Patent:
7,969,248 →
Application:
12/512,961 →
Distributed Front-End Fifo for Source-Synchronous Interfaces with Non-Continuous Clocks
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12/538,810 →
Current Mode Circuitry to Modulate a Common Mode Voltage
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12/561,140 →
Redundant Configuration Memory Systems and Methods
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12/564,781 →
Messaging to Provide Data Link Integrity
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8,122,277 →
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12/578,470 →
Clock Distribution Chip
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Application:
12/578,492 →
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Shallow Trench Isolation (Sti) with Trench Liner of Increased Thickness
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7,985,656 →
Application:
12/607,333 →
Shallow Trench Isolation (Sti) with Trench Liner of Increased Thickness
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12/607,868 →
Flash Memory Array with Independently Erasable Sectors
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8,059,470 →
Application:
12/611,262 →
Programmable Logic Device with Built in Self Test
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7,944,765 →
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12/626,289 →
Programmable Logic Device and Methods for Providing Multi-Boot Configuration Data Support
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Application:
12/630,163 →
Power Delivery Over Digital Interaction Interface for Video and Audio (Diiva)
Combined Variable Gain Amplifier and Analog Equalizer Circuit
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12/637,884 →
Separate Configuration of I/O Cells and Logic Core in a Programmable Logic Device
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Application:
12/698,283 →
Block Noise Detection and Filtering
Hybrid Interface for Serial and Parallel Communication
Method and Devices for Storing a Security Key Using Programmable Fuses
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7,834,652 →
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12/709,685 →
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Video Frame Synchronization
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12/729,952 →
Configuring Multiple Programmable Logic Devices with Serial Peripheral Interfaces
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8,384,427 →
Application:
12/752,455 →
Bondwire Configuration for Reduced Crosstalk
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12/757,087 →
Programmable Logic Device Programming Verification Systems and Methods
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8,108,754 →
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12/786,359 →
Shared-Array Multiple-Output Digital-to-Analog Converter
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8,164,499 →
Application:
12/813,540 →
Delaying Data Signals
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8,441,292 →
Application:
12/813,573 →
Mechanism for Memory Reduction in Picture-in-Picture Video Generation
Soft Error Upset Hardened Integrated Circuit Systems and Methods
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7,868,646 →
Application:
12/818,544 →
Mechanism for Internal Processing of Content Through Partial Authentication on Secondary Channel
Mechanism for Partial Encryption of Data Streams
17B/20B Coding System
Multi-View Display System
Composite Wire Indexing for Programmable Logic Devices
Patent:
8,286,116 →
Application:
12/871,764 →
De-Encapsulation of Data Streams into Multiple Links
Combining Video Data Streams of Differing Dimensionality for Concurrent Display
Displacement Sensing Using a Flexible Substrate
Discovery of Electronic Devices in a Combined Network
Bitline Floating Circuit for Memory Power Reduction
Patent:
8,351,287 →
Application:
12/976,412 →
Triggered Sense Amplifier
Patent:
8,477,549 →
Application:
12/976,520 →
Blocking Memory Readback In A Programmable Logic Device
Patent:
8,522,126 →
Application:
12/977,011 →
Adaptive Interconnection Scheme for Multimedia Devices
Serializer with Odd Gearing Ratio
Patent:
8,274,412 →
Application:
12/987,393 →
Transmission and Detection of Multi-Channel Signals in Reduced Channel Format
Pre-Configuration Programmability of I/O Circuitry
Patent:
8,384,428 →
Application:
13/006,622 →
Programmable Buffer
Patent:
8,324,934 →
Application:
13/007,688 →
Low-Power, Glitch-Less, Configurable Delay Element
Patent:
8,248,136 →
Application:
13/007,804 →
Determination of Physical Connectivity Status of Devices Based on Electrical Measurement
Wire Mapping for Programmable Logic Devices
Patent:
8,104,009 →
Application:
13/026,555 →
Compression and Decompression of Configuration Data Using Repeated Data Frames
Patent:
8,058,898 →
Application:
13/034,174 →
Low-Voltage Current Sense Amplifier
Patent:
8,654,600 →
Application:
13/037,703 →
Programmable Logic Device Wakeup Using a General Purpose Input/Output Port
Patent:
8,368,424 →
Application:
13/038,259 →
Variable Response Mode for Synchronous Data Read
Patent:
8,816,718 →
Application:
13/038,270 →
Voltage Discharge Circuit Having Divided Discharge Current
Patent:
8,553,463 →
Application:
13/052,142 →
Safe Programming of Key Information into Non-Volatile Memory for a Programmable Logic Device
Patent:
8,319,521 →
Application:
13/076,300 →
Power Control Block with Output Glitch Protection
Patent:
8,314,634 →
Application:
13/079,578 →
Phase Locked Loop Circuit with Selectable Feedback Paths
Patent:
8,531,222 →
Application:
13/079,595 →
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Audio and Video Data Multiplexing for Multimedia Stream Switch
Edge Detection
Flexible Updating of Multi-Bit Registers
Patent:
8,441,284 →
Application:
13/154,885 →
Voltage Regulators with a Shared Capacitor
Patent:
8,547,075 →
Application:
13/155,547 →
Integrated Circuit Design Software with Cross Probing Between Tool Graphical User Interfaces (Guis)
Patent:
8,555,217 →
Application:
13/164,108 →
Mechanism for Facilitating Fine-Grained Self-Refresh Control for Dynamic Memory Devices
Configurable Multi-Dimensional Driver and Receiver
Single-Ended Configurable Multi-Mode Driver
Alignment Circuit for Parallel Data Streams
Patent:
8,495,264 →
Application:
13/178,536 →
Simultaneous Development of Complementary Ic Families
Patent:
8,539,409 →
Application:
13/178,599 →
Method and System for Placing Integrated Circuits into Predominantly Ultra-Low Voltage Mode for Standby Purposes
Patent:
8,314,632 →
Application:
13/193,984 →
Conversion of Multimedia Data Streams for Use by Connected Devices
Dual-Port Sram with Bit Line Clamping
Patent:
8,451,679 →
Application:
13/212,121 →
Identification and Handling of Data Streams Using Coded Preambles
Comparator with Jitter Mitigation
Patent:
8,169,237 →
Application:
13/275,102 →
Testing of Soft Error Detection Logic for Programmable Logic Devices
Patent:
8,370,691 →
Application:
13/299,507 →
Multimedia I/O System Architecture for Advanced Digital Television
Mechanism for Clock Recovery for Streaming Content Being Communicated Over a Packetized Communication Network
Application:
13/339,339 →
Publication:
US 2012/0182473
Proxy Device Operation in Command and Control Network
Mechanism for Low Power Standby Mode Control Circuit
Programmable Logic Device Data Rate Booster for Digital Signal Processing
Patent:
8,977,885 →
Application:
13/412,408 →
Method, Apparatus and System for Transitioning an Audio/Video Device Between a Source Mode and a Sink Mode
In-System Reconfigurable Circuit for Mapping Data Words of Different Lengths
Patent:
8,823,561 →
Application:
13/452,060 →
Video Management and Control in Home Multimedia Network
Automated Service Discovery and Dynamic Connection Management
Transmission of Multiple Protocol Data Elements via an Interface Utilizing a Data Tunnel
Low-Power Configurable Delay Element
Patent:
8,461,894 →
Application:
13/585,142 →
Test Solution for Ring Oscillators
Combining Video and Audio Streams Utilizing Pixel Repetition Bandwidth
Serializer with Multiple Stages
Patent:
8,912,933 →
Application:
13/616,173 →
Interfacing Between Integrated Circuits with Asymmetric Voltage Swing
Triple-Trim Reference Voltage Generator
Patent:
8,710,898 →
Application:
13/653,827 →
Methods and Apparatuses to Provide an Electro-Optical Alignment
Placing Integrated Circuits into Low Voltage Mode for Standby Purposes
Patent:
8,643,398 →
Application:
13/680,947 →
Multi-Channel Transmitter Synchronization Circuitry
Patent:
9,819,478 →
Application:
13/681,782 →
Integrated Circuit Package with Input Capacitance Compensation
Patent:
8,643,168 →
Application:
13/685,385 →
In-System Margin Measurement Circuit
Patent:
8,686,773 →
Application:
13/721,867 →
Mechanism for Facilitating Dynamic Timestamp-Less Clock Generation for Transmitting Media Streams Over Shared Channels
Hybrid H-Bridge and Cml Driver
Patent:
8,797,064 →
Application:
13/738,265 →
Communication Bridging Between Devices via Multiple Bridge Elements
Configurable Single-Ended Driver
Transmitting Multiple Differential Signals Over a Reduced Number of Physical Channels
Apparatus, System and Method for Providing Clock and Data Signaling
Leakage-Current Abatement Circuitry for Memory Arrays
Mechanism for Facilitating Synchronization of Audio and Video Between Multiple Media Devices
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Full-Frame Buffer to Improve Video Performance in Low-Latency Video Communication Systems
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Integrated Circuit with Pin for Setting Digital Address
Patent:
8,786,482 →
Application:
13/857,919 →
Highly Secure and Extensive Scan Testing of Integrated Circuits
Loss of Signal Detection for High-Speed Serial Links
Method, Apparatus and System for Communicating Sideband Data with Non-Compressed Video
Patent:
8,786,776 →
Application:
13/891,842 →
Delaying Data Signals
Block Noise Detection and Filtering
Dual-Port Sram with Bit Line Clamping
Configuration Sequence for Programmable Logic Device
Multiple Protocol Tunneling Using Time Division Operations
Network Repository for Metadata
Hybrid Interface for Serial and Parallel Communication
Integrated Mobile Desktop
Stable Supply-Side Reference Over Extended Voltage Range With Hot-Plugging Compatibility
Discovery of Electronic Devices in a Combined Network
Elements to Counter Transmitter Circuit Performance Limitations
Dynamic Power Supply Switching for Clocking Signals
Patent:
8,829,944 →
Application:
14/040,955 →
Serdes Interface Architecture for Multi-Processor Systems
Configuration of Selected Modules of a Hardware Block Within a Programmable Logic Device
System, Method, and Apparatus for Smoothing of Edges in Images to Remove Irregularities
Smart Scalable Storage Switch Architecture
On Screen Displays Associated with Remote Video Source Devices
Partially Depopulated Interconnection Arrays for Packaged Semiconductor Devices and Printed Circuit Boards
Multi-View Display System
Esd Protection Using Shared Rc Trigger
Mechanism for Facilitating Dynamic Phase Detection with High Jitter Tolerance for Images of Media Streams
Compensation Scheme for Mhl Common Mode Clock Swing
Line Driver with Separate Pre-Driver for Feed-Through Capacitance
Driving Data of Multiple Protocols Through a Single Set of Pins
Formatting Audio-Video Information Compliant with First Transmission Format to Second Transmission Format in Integrated Circuit for Offloading Physical Layer Logic for First Transmission Format to Separate Integrated Circuit
Group Based Routing in Programmable Logic Device
Messaging to Provide Data Link Integrity
Mechanism for Memory Reduction in Picture-in-Picture Video Generation
Hot-Socket Circuitry
Mechanism for Facilitating Dynamic Counter Synchronization and Packetization in High-Definition Multimedia Interface and Mobile High-Definition Link
Apparatus, System and Method for Providing Switching with a T-Coil Circuit
Apparatus, Method and System for Asymmetric, Full-Duplex Communication
Collector Current Driver for a Bipolar Junction Transistor Temperature Transducer
Low-Voltage Current Sense Amplifer
Test Solution for a Random Number Generator
Component Placement with Repacking for Programmable Logic Devices
Calibration of Single-Ended High-Speed Interfaces
Calibration of Single-Ended High-Speed Interfaces
Method and Apparatus for Implementing Wide Data Range and Wide Common-Mode Receivers
Communicating with MIPI-Compliant Devices Using Non-MIPI Interfaces
Communicating with MIPI-Compliant Devices Using Non-MIPI Interfaces
Patent:
9,009,379 →
Application:
14/223,096 →
Transistor Matching for Generation of Precise Current Ratios
Communication of Multimedia Data Streams over Multiple Communication Lanes
Semiconductor Defect Characterization
Partition Based Design Implementation for Programmable Logic Devices
Transmission and Detection of Multi-Channel Signals in Reduced Channel Format
Encoding Guard Band Data For Transmission Via A Communications Interface Utilizing Transition-Minimized Differential Signaling (Tmds) Coding
Authentication Engine and Stream Cipher Engine Sharing in Digital Content Protection Architectures
Embedded Memory Testing Using Back-To-Back Write/Read Operations
Transmitting Apparatus with Source Termination
Configurable Multi-Dimensional Driver and Receiver
PVT Compensation Scheme for Output Buffers
Holdtime Correction Using Input/Output Block Delay
Efficient Constant Multiplier Implementation for Programmable Logic Devices
Incrementer Absorption into Multiplier Logic for Programmable Logic Devices
Patent:
9,152,753 →
Application:
14/319,481 →
Sram with Two-Level Voltage Regulator
Mixed-Width Memory Techniques for Programmable Logic Devices
System-Level Dual-Boot Capability in Systems Having One or More Devices Without Native Dual-Boot Capability
Bus-Based Clock to Out Path Optimization
Caching of Capabilities Information of Counterpart Device for Efficient Handshaking Operation
Charge Pump Calibration for Dual-Path Phase-Locked Loop
Linear Regulator with Improved Power Supply Ripple Rejection
Techniques for Fractional-N Phase Locked Loops
Frequency Response Compensation in a Digital to Analog Converter
Phase Locked Loop with Sub-harmonic Locking Prevention Functionality
Spectrum Shaping Voltage to Current Converter
Radio Frequency Interference Reduction In Multimedia Interfaces
Compressed Blanking Period Transfer Over a Multimedia Link
Arbitration Signaling Within a Multimedia High Definition Link (Mhl 3) Device
Phase Relationship Control for Control Channel of a Multimedia Communication Link
Retry Disparity for Control Channel of a Multimedia Communication Link
Inter-Device Conflict Resolution on a Multimedia Link
Logic Absorption Techniques for Programmable Logic Devices
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Class Ab Amplifier with Programmable Quiescent Current
Programmable Filter
Patent:
9,325,302 →
Application:
14/558,851 →
Determination of Physical Connectivity Status of Devices Based on Electrical Measurement
Electrical Duplex to Optical Conversion
Mechanism for Facilitating Dynamic Phase Detection with High Jitter Tolerance for Images of Media Streams
Reconfigurable and Scalable Hardware Management Architecture
System for Dynamic Audio Visual Capabilities Exchange
Control Target Selection
Displaying Multiple Videos on Sink Device Using Display Information of Source Device
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Stream Creation with Limited Topology Information
Stream Creation with Limited Topology Information
Stream Creation with Limited Topology Information
Registers for Post Configuration Testing of Programmable Logic Devices
Hotswap Operations for Programmable Logic Devices
Flexible Ripple Mode Device Implementation for Programmable Logic Devices
Multiple Mode Device Implementation for Programmable Logic Devices
Efficient Routing of Streams Encrypted Using Point-to-Point Authentication Protocol
High Speed Complementary Nmos Lut Logic
Shared Logic for Multiple Registers with Asynchronous Initialization
Media Stream Data and Control Parameter Synchronization
Secure Internal Control for Encrypting Video Data
Adaptive Processing of Video Streams with Reduced Color Resolution
HDMI Connector
Port Processor Capable of Performing Authentication for Multiple Source Devices
Bidirectional Transmission Of USB Data Using Audio/Video Data Channel
Network Topology Discovery
Programmable Circuits for Correcting Scan-Test Circuitry Defects in Integrated Circuit Designs
Clock Placement for Programmable Logic Devices
Method for Synchronizing A/V Streams
Area-Efficient Memory Mapping Techniques for Programmable Logic Devices
Delay Specific Routings for Programmable Logic Devices
Single-Ended Configurable Multi-Mode Driver
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Crowbar Current Elimination
High-Resolution Oscillator Having Wide Frequency Range
Patent:
9,490,778 →
Application:
14/797,206 →
Elements to Counter Transmitter Circuit Performance Limitations
Dynamic Control of Pixel Color Formats Used to Encode Color Video Streams
Application:
14/868,985 →
Publication:
US 2017/0094289
Adaptive Technique for Adjusting Signal Development Across Bit Lines for Read Operation Robustness in Memory Circuits
Patent:
9,530,486 →
Application:
14/876,862 →
Memory Circuit Having Non-Volatile Memory Cell and Methods of Using
Leakage-Current Abatement Circuitry for Memory Arrays
Metadata Transfer in Audio Video Systems
Patent:
9,769,417 →
Application:
14/928,921 →
Segmented Error Coding for Block-Based Memory
Maintaining Synchronization of Encryption Process Across Devices By Sending Frame Numbers
Early Global Set/Reset Signal Determination for Programmable Logic Devices
Patent:
9,680,475 →
Application:
15/073,583 →
Multiplexer Reduction for Programmable Logic Devices
Partially Depopulated Interconnection Arrays for Packaged Semiconductor Devices and Printed Circuit Boards
Driving Data of Multiple Protocols Through a Single Set Of Pins
Method of Transmitting and Receiving Audio Signals and Apparatus Thereof
Echo Cancellation for High Speed Full Duplex Data Transmissions
Devices and Methods for Remote Control of Target Devices
Application:
15/321,673 →
Publication:
US 2017/0221351
Acoustic Gesture Recognition Systems and Methods
Communication of Multimedia Data Streams Over Multiple Communication Lanes
Stream Creation With Limited Topology Information
Transmission And Detection Of Multi-Channel Signals In Reduced Channel Format
Secure Internal Control for Encrypting Video Data
Deterministic Read Back and Error Detection for Programmable Logic Devices
Interconnect for Micro Form-Factor Photonic
Application:
15/488,291 →
Publication:
US 2017/0302387
Timing Based Corrector for Video
Digital Content Protection Over Audio Return Data Link
Stream Creation with Limited Topology Information
Selective Power Gating of Routing Resource Configuration Memory Bits for Programmable Logic Devices
Patent:
10,079,054 →
Application:
15/614,419 →
Flexible Ripple Mode Device Implementation for Programmable Logic Devices
Multiple Mode Device Implementation for Programmable Logic Devices
Clock Recovery and Data Recovery for Programmable Logic Devices
Clock Recovery and Data Recovery for Programmable Logic Devices
Multi-Time Programmable Non-Volatile Memory Cell
Compressed Blanking Period Transfer Over a Multimedia Link
Low-Speed Bus Time Stamp Methods and Circuitry
Network Repository for Metadata
Transmitting Common Mode Control Data Over Audio Return Channel
Multimedia Communication Bridge
Spectrum Shaping Voltage to Current Converter
Memory Circuit Having Non-Volatile Memory Cell and Methods of Using
Patent:
48,625 →
Application:
15/975,506 →
Polarization converter systems and methods
Patent:
10,484,036 →
Application:
15/999,631 →
Direct Digital Synthesis Systems and Methods
Hysteresis Control Systems and Methods for Programmable Logic Devices
Memory Circuit Having Non-Volatile Memory Cell and Methods of Using
Forward Error Correction and Asymmetric Encoding for Video Data Transmission Over Multimedia Link
Application:
16/090,165 →
Publication:
US 2019/0115935
Polarization Filter Systems and Methods
Patent:
10,484,117 →
Application:
16/103,720 →
Multiple Mode Device Implementation for Programmable Logic Devices
Hybrid Universal Serial Bus Interconnect for Micro Form-Factor Photonics
Application:
16/221,428 →
Publication:
US 2019/0137710
Fast Boot Systems and Methods for Programmable Logic Devices
Memory Circuit Having Non-Volatile Memory Cell and Methods of Using
Patent:
48,570 →
Application:
16/267,278 →
Method of Transmitting and Receiving Audio Signals and Apparatus Thereof
Multi-Time Programmable Non-Volatile Memory Cell
Low Latency Interrupt Alerts for Artificial Neural Network Systems and Methods in Data Stream Processing
Devices with Programmable Logic and Security Features and Methods of Using
Application:
62/670,487 →
Polarization Converter Systems and Methods
Application:
62/687,731 →
Polarization Filter Systems and Methods
Application:
62/687,787 →
Key Provisioning Systems and Methods for Programmable Logic Devices
Application:
62/756,001 →
Failure Characterization Systems and Methods for Programmable Logic Devices
Application:
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Asset Management Systems and Methods for Programmable Logic Devices
Application:
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