Pre-configuration programmability of I/O circuitry

1. A programmable logic device comprising:

programmable input/output (I/O) circuitry having a plurality of programmable I/O circuits connected to corresponding I/O pads;

a programmable logic core connected to receive incoming signals from and provide outgoing signals to the I/O circuitry;

configuration memory connected to store configuration data for programming the I/O circuitry and the logic core; and

a configuration controller adapted to support configuration of the programmable logic device by an external configuration interface,

wherein at least one programmable I/O circuit comprises:

I/O component circuitry adapted to receive incoming signals from and provide outgoing signals to a corresponding I/O pad of the programmable logic device; and

I/O control circuitry responsive to the configuration controller to program the I/O circuit on power up into a first I/O operating mode for receiving the configuration data from the configuration interface and storing the data into the configuration memory and then into a second I/O operating mode based on the stored configuration data.

2. The invention of claim 1 , wherein the I/O component circuitry comprises:

an output driver adapted to apply an output signal at the corresponding I/O pad;

an input receiver adapted to receive an input signal applied to the I/O pad;

a keeper circuit adapted to prevent voltage level at the I/O pad from floating; and

termination circuitry adapted to apply a termination impedance to the I/O pad.

3. The invention of claim 1 , wherein the I/O control circuitry is further responsive to the configuration controller to change the first I/O operating mode of the I/O circuit multiple times before the receiving and storing of the configuration data is complete.

4. The invention of claim 1 , wherein the I/O control circuitry is adapted to selectively apply, to the I/O component circuitry, (i) I/O mode-control signals received from the configuration memory or (ii) I/O mode-control signals received from the configuration controller, to control the operating mode of the I/O circuit.

5. The invention of claim 4 , wherein the I/O control circuitry receives one or more selection-control signals from the configuration controller to control the selection of the I/O mode-control signals.

6. The invention of claim 5 , wherein the configuration controller is adapted to generate and apply multiple selection-control signals to the I/O control circuit to enable one or more I/O mode-control signals received from the configuration memory and one or more I/O mode-control signals received from the configuration controller to be simultaneously selected to control the operating mode of the I/O circuit.

7. The invention of claim 1 , wherein different operating modes for the I/O circuit comprise two or more of pull up mode, pull down mode, and tristate mode.

8. The invention of claim 1 , wherein different operating modes for the I/O circuit comprise different pull mode strengths.

9. The invention of claim 1 , wherein different operating modes for the I/O circuit comprise two or more of push pull mode, open drain mode, and differential mode.

10. The invention of claim 1 , wherein the I/O control circuitry enables the I/O circuit to be programmed in different operating modes corresponding to different configuration interfaces such that the I/O circuit can be programmed to support the configuration of the programmable logic device via the corresponding I/O pad using any one of the different configuration interfaces.

11. The invention of claim 1 , wherein the I/O control circuitry comprises at least one multiplexer connected to receive (i) an I/O mode-control signal from the configuration memory, (ii) an I/O mode-control signal from the configuration controller and (iii) a selection-control signal from the configuration controller and to output one of the I/O mode-control signals based on the value of the I/O selection-control signal, wherein the selected I/O mode-control signal is used in programming the I/O circuit into one of the plurality of operating modes.

12. The invention of claim 11 , wherein the I/O control circuitry comprises a plurality of said multiplexers, wherein:

at least two multiplexers are connected to receive different I/O selection-control signals from the configuration controller; and

the configuration controller is adapted to independently and simultaneously generate the different I/O selection-control signals such that a first multiplexer selects the corresponding I/O mode-control signal from the configuration memory and a second multiplexer selects the corresponding I/O mode-control signal from the configuration controller.

13. The invention of claim 1 , wherein signals, applied to a plurality of user mode pads of the programmable logic device by the configuration interface, identify interface signaling requirements to be supported by I/O circuits corresponding to other I/O pads connected to the configuration interface.

14. The invention of claim 13 , wherein the configuration controller generates and applies, to the I/O control circuit, I/O mode-control signals corresponding to the interface signaling requirements of the configuration interface.

15. The invention claim 1 , wherein a single set of I/O pads are used to configure the programmable logic device using any of a plurality of different types of external configuration interfaces having different sets of interface signaling requirements.

16. The invention of claim 1 , wherein the programmable logic device is a field-programmable gate array (FPGA).

17. The invention of claim 1 , wherein:

the I/O control circuitry is further adapted to program the operating mode of the I/O circuit after the completion of the configuration of the programmable logic device based on the configuration data stored in the configuration memory;

the operating mode of the I/O circuit after the completion of the configuration of the programmable logic device is different from the operating mode of the I/O circuit before the completion of the configuration of the programmable circuit;

the I/O control circuitry is adapted to change the operating mode of the I/O circuit multiple times before the completion of the configuration of the programmable logic device;

the I/O control circuitry is adapted to selectively apply, to the I/O component circuitry, (i) I/O mode-control signals received from the configuration memory or (ii) I/O mode-control signals received from the configuration controller, to control the operating mode of the I/O circuit;

the I/O control circuitry receives one or more selection-control signals from the configuration controller to control the selection of the I/O mode-control signals;

the configuration controller is adapted to generate and apply multiple selection-control signals to the I/O control circuit to enable one or more I/O mode-control signals received from the configuration memory and one or more I/O mode-control signals received from the configuration controller to be simultaneously selected to control the operating mode of the I/O circuit;

the I/O control circuitry enables the I/O circuit to be programmed in different operating modes corresponding to different configuration interfaces such that the I/O circuit can be programmed to support the configuration of the programmable logic device via the corresponding I/O pad using any one of the different configuration interfaces;

the I/O control circuitry comprises at least one multiplexer connected to receive (i) an I/O mode-control signal from the configuration memory, (ii) an I/O mode-control signal from the configuration controller and (iii) a selection-control signal from the configuration controller and to output one of the I/O mode-control signals based on the value of the I/O selection-control signal, wherein the selected I/O mode-control signal is used in programming the I/O circuit into one of the plurality of operating modes;

the I/O control circuitry comprises a plurality of said multiplexers, wherein:

at least two multiplexers are connected to receive different I/O selection-control signals from the configuration controller; and

the configuration controller is adapted to independently and simultaneously generate the different I/O selection-control signals such that a first multiplexer selects the corresponding I/O mode-control signal from the configuration memory and a second multiplexer selects the corresponding I/O mode-control signal from the configuration controller;

signals, applied to a plurality of user mode pads of the programmable logic device by the configuration interface, identify interface signaling requirements to be supported by I/O circuits corresponding to other I/O pads connected to the configuration interface;

the configuration controller generates and applies, to the I/O control circuit, I/O mode-control signals corresponding to the interface signaling requirements of the configuration interface;

a single set of I/O pads are used to configure the programmable logic device using any of a plurality of different types of external configuration interfaces having different sets of interface signaling requirements; and

the programmable logic device is a field-programmable gate array (FPGA).

18. A method of configuring a programmable logic device (PLD) comprising:

powering up the PLD;

receiving and interpreting within the PLD mode-pad signals that identify a type of configuration interface connected to the PLD;

programming an I/O circuit of the PLD into a first I/O operating mode for receiving configuration data from the identified configuration interface;

receiving the configuration data through the I/O circuit and storing the data within configuration memory of the PLD; and

reprogramming the I/O circuit into a second I/O operating mode based on the stored configuration data.