Patent Assignment
Reel/Frame 049827/0326
Release of Security Interest
Recorded: 2019-05-21
Pages: 131
Assignor
JEFFERIES FINANCE LLC
Executed: 2019-05-17
Assignees
LATTICE SEMICONDUCTOR CORPORATION
5555 NE MOORE CT, HILLSBORO, OREGON, 97124
SILICON IMAGE, INC.
5555 NE MOORE CT, HILLSBORO, OREGON, 97124
SIBEAM, INC.
5555 NE MOORE CT, HILLSBORO, OREGON, 97124
DVDO, INC.
5555 NE MOORE CT, HILLSBORO, OREGON, 97124
Covered Properties
(1140)
High Speed First-in-First-Out Memory
Patent:
4,642,797 →
Application:
06/551,735 →
Programmable Logic Device with Limited Sense Currents and Noise Isolation
Patent:
4,833,646 →
Application:
06/707,670 →
In-System Programmable Logic Device
Patent:
4,879,688 →
Application:
06/862,815 →
Programmable Logic Array
Patent:
4,766,569 →
Application:
06/871,063 →
One-Time Programmable Data Security System for Programmable Logic Device
Patent:
4,887,239 →
Application:
06/882,602 →
Programmable Data Security Circuit for Programmable Logic Device
Patent:
4,852,044 →
Application:
07/236,348 →
Programmable Logic Device Configurable Input/Output Cell
Patent:
4,896,296 →
Application:
07/288,945 →
Interconnect Structure for Programmable Logic Device
Patent:
5,255,203 →
Application:
07/538,211 →
Fully Configurable Versatile Field Programmable Function Element
Patent:
5,255,221 →
Application:
07/679,370 →
Non-Volatile Erasable and Programmable Interconnect Cell
Patent:
5,251,169 →
Application:
07/696,453 →
Tunable Voltage Reference Circuit to Provide an Output Voltage with a Predetermined Temperature Coefficient Independent of Variation in Supply Voltage
Patent:
5,281,906 →
Application:
07/785,442 →
Temperature Compensated Cmos Voltage to Current Converter
Patent:
5,231,316 →
Application:
07/853,453 →
Active Clamp Circuit Scheme for Cmos Devices
Patent:
5,357,156 →
Application:
07/911,841 →
Arrangement for Parallel Programming of in-System Programmable Ic Logic Devices
Patent:
5,329,179 →
Application:
07/957,311 →
Programmable Integrated-Circuit Switch
Patent:
5,452,229 →
Application:
07/993,711 →
Single Polysilicon Layer E2PROM Cell
Patent:
5,418,390 →
Application:
08/033,934 →
Sense Amplifiers and Sensing Methods
Patent:
5,394,037 →
Application:
08/042,533 →
Multiplexed Control Pins for in-System Programming and Boundary Scan State Machines in a High Density Programmable Logic Device
Patent:
5,412,260 →
Application:
08/106,263 →
Programmable Semiconductor Antifuse Structure and Method of Fabricating
Patent:
5,353,246 →
Application:
08/108,363 →
Input Routing Pool
Patent:
5,404,055 →
Application:
08/115,533 →
Structure and Method for Implementing Hierarchical Routing Pools in a Programmable Logic Circuit
Patent:
5,394,033 →
Application:
08/115,723 →
Single Polysilicon Layer Flash E2PROM Cell
Patent:
5,886,378 →
Application:
08/179,887 →
Output Enable Structure and Method for a Programmable Logic Device
Patent:
5,506,517 →
Application:
08/342,675 →
Continuous Time Programmable Analog Block Architecture
Patent:
5,574,678 →
Application:
08/396,994 →
Active Resistor for Stability Compensation
Patent:
5,617,064 →
Application:
08/403,352 →
Low Distortion Differential Transconductor Output Current Mirror
Patent:
5,493,205 →
Application:
08/403,354 →
Cmos Programmable Resistor-Based Transconductor
Patent:
5,510,738 →
Application:
08/403,359 →
Vbb Reference for Pumped Substrates
Patent:
5,670,907 →
Application:
08/403,595 →
Constant Delay Interconnect for Coupling Configurable Logic Blocks
Patent:
5,490,074 →
Application:
08/423,303 →
Cmos Memory Cell with Gate Oxide of Both Nmos and Pmos Transistors as Tunneling Window for Program and Erase
Patent:
5,596,524 →
Application:
08/427,117 →
Cascode Array Cell Partitioning for a Sense Amplifier of a Programmable Logic Device
Patent:
5,491,433 →
Application:
08/444,306 →
Completely Complementary Mos Memory Cell with Tunneling Through the Nmos and Pmos Transistors During Program and Erase
Patent:
5,594,687 →
Application:
08/447,991 →
Method of Making a Spacer Based Antifuse Structure for Low Capacitance and High Reliability
Patent:
5,756,367 →
Application:
08/449,384 →
Lead Frame with Noisy and Quiet V and V Leads Ss Dd
Patent:
5,570,046 →
Application:
08/453,184 →
Ground Bounce Isolated Output Buffer Polarity Control Circuit Which May Be Used W3ITH a Ground Bounce Limiting Buffer
Patent:
5,583,451 →
Application:
08/453,479 →
Programmable Logic Device with Internal Time-Constant Multiplexing of Signals from External Interconnect Buses
Patent:
5,621,650 →
Application:
08/456,946 →
Macrocell and Clock Signal Allocation Circuit for a Programmable Logic Device (Pld) Enabling Pld Resources to Provide Multiple Functions
Patent:
5,589,782 →
Application:
08/458,865 →
Multi-Tiered Hierarchical High Speed Switch Matrix Structure for Very High-Density Complex Programmable Logic Devices
Patent:
5,818,254 →
Application:
08/459,230 →
Programmable Uniform Symmetrical Distribution Logic Allocator for a High-Density Complex Pld
Patent:
5,781,030 →
Application:
08/459,234 →
Programmable Optimized-Distribution Logic Allocator for a High-Density Complex Pld
Patent:
6,531,890 →
Application:
08/459,570 →
P-Type Flip-Flop
Patent:
5,638,018 →
Application:
08/459,786 →
Very High-Density Complex Programmable Logic Devices with a Multi-Tiered Hierarchical Switch Matrix and Optimized Flixible Logic Allocation
Patent:
5,521,529 →
Application:
08/459,960 →
Array of Configurable Logic Blocks Including Cascadable Lookup Tables
Patent:
5,586,044 →
Application:
08/461,196 →
Array of Configurable Logic Blocks Each Including a First Lookup Table Output Coupled to Selectively Replace an Output of Second Lookup with an Alternate Function Output
Patent:
5,469,368 →
Application:
08/462,934 →
Low Power Cmos Array Cell for a Pld with Program and Erase Using Controlled Avalanche Injection
Patent:
5,754,471 →
Application:
08/466,438 →
System for Synthesizing Field Programmable Gate Array Implementations from High Level Circuit Descriptions
Patent:
5,594,657 →
Application:
08/473,620 →
An I/O Macrocell for a Programmable Logic Device
Patent:
5,612,631 →
Application:
08/474,629 →
Flexible Synchronous/Asynchronous Cell Structure for a High Density Programmable Logic Device
Patent:
5,811,986 →
Application:
08/474,635 →
A High Density Programmable Logic Device
Patent:
5,869,981 →
Application:
08/479,872 →
Multiple Array Programmable Logic Device with a Plurality of Programmable Switch Matrices
Patent:
5,617,042 →
Application:
08/483,623 →
A Flexible Block Clock Generation Circuit for Providing Clock Signals to Clocked Elements in a Multiple Array High Density Programmable Logic Divice
Patent:
5,594,365 →
Application:
08/486,174 →
Family of Multiple Segmented Programmable Logic Blocks Interconnected by a High Speed Centralized Switch Matrix
Patent:
5,764,078 →
Application:
08/486,178 →
Method and Apparatus for Converting Field-Programmable Gate Array Implementations into Mas-Programmable Logic Cell Implementations
Patent:
5,526,278 →
Application:
08/492,604 →
Isolation Using Self-Aligned Trench Formation and Conventional Locos
Patent:
5,679,599 →
Application:
08/493,640 →
Voltage Range Tolerant Cmos Output Buffer with Reduced Input Capacitance
Patent:
5,565,794 →
Application:
08/494,271 →
Non-Volatile Memory Cells Using Only Positive Charge to Store Data
Patent:
5,742,542 →
Application:
08/497,992 →
Method for Screening Non-Volatile Memory and Programmable Logic Devices
Patent:
5,700,698 →
Application:
08/500,295 →
Field Implant for Semiconductor Device
Patent:
5,604,370 →
Application:
08/501,230 →
Method for Simultaneous Programming of in-System Programmable Integrated Circuits
Patent:
5,635,855 →
Application:
08/505,837 →
Programmable Function Unit as Parallel Multiplier Cell
Patent:
5,570,039 →
Application:
08/507,893 →
Field Programmable Gate Array with Multi-Port Ram
Patent:
5,559,450 →
Application:
08/507,957 →
Interlaced Layout Configuration for Differential Pairs of Interconnect Lines
Patent:
5,581,126 →
Application:
08/528,030 →
Low-Skew Signal Routing in a Programmable Array
Patent:
5,528,170 →
Application:
08/535,362 →
Control Gate-Addressed Cmos Non-Volatile Cell That Programs Through Gates of Cmos Transistors
Patent:
5,615,150 →
Application:
08/551,974 →
Cmos Eeprom Cell with Tunneling Window in the Read Path
Patent:
5,587,945 →
Application:
08/554,092 →
Memory Cell for a Programmable Logic Device (Pld) Avoiding Pumping Programming Voltage Above an Nmos Threshold
Patent:
5,666,309 →
Application:
08/560,038 →
Array of Configurable Logic Blocks Each Including a Lookup Table Having Inputs Coupled Toa First Multiplexer and Having Outputs to a Second Multiplexer
Patent:
5,587,921 →
Application:
08/560,933 →
Method of Forming Multiple Gate Oxide Thicknesses on a Wafer Substrate
Patent:
5,672,521 →
Application:
08/561,306 →
Micropprocessor System with Process Identification Tag Entries to Reduce Cache Flushing After a Context Switch
Patent:
5,809,522 →
Application:
08/573,622 →
Deconvolution Input Buffer Compensating for Capacitance of a Switch Matrix of a High Density Programmable Logic Device
Patent:
5,739,713 →
Application:
08/574,776 →
Lock Generator Circuit for Use with a Dual Edge Register That Provides a Separate Enable for Each Edge of an Input Clock Signal
Patent:
5,719,516 →
Application:
08/575,852 →
Capacitance Elimination Circuit Which Provides Current to a Node in a Circuit to Eliminate the Effect of Parasitic Capacitance at the Node
Patent:
5,736,888 →
Application:
08/575,898 →
Array of Configurable Logic Blocks Including Network Means for Broadcasting Clock Signals to Different Pluralities of Logic Blocks
Patent:
5,598,346 →
Application:
08/596,679 →
Field Programmable Gate Array with Write-Port Enabled Memory
Patent:
5,623,217 →
Application:
08/606,702 →
Segment Descriptor Cache for a Processor
Patent:
5,926,841 →
Application:
08/614,728 →
Cmos Memory Cell with Tunneling During Program and Erase Through the Nmos and Pmos Transistors and a Pass Gate Separating the Nmos and Pmos Transistors
Patent:
5,646,901 →
Application:
08/625,403 →
Parallel Programming of in-System (Isp) Programmable Devices Using an Automatic Tester
Patent:
5,751,163 →
Application:
08/632,811 →
Active Resistor for Stability Compensation
Patent:
5,666,087 →
Application:
08/635,184 →
Method and Apparatus for in-System Programming of a Programmable Logic Device Using a Two-Wire Interface
Patent:
5,864,486 →
Application:
08/643,291 →
Array Cell Circuit with Split Read/Write Line
Patent:
5,748,525 →
Application:
08/643,807 →
A Method for Providing a Plurality of Hierarchical Signal Paths in a Very High-Density Programmable Logic Device
Patent:
5,789,939 →
Application:
08/653,186 →
Enclosure for Removable Computer Peripheral Equipment
Patent:
6,018,456 →
Application:
08/656,032 →
Field Programmable Gate Array (Fpga) with Interconnect Encoding
Patent:
5,723,984 →
Application:
08/659,279 →
Field Programmable Gate Array (Fpga) Having an Improved Configuration Memory and Look Up Table
Patent:
5,808,942 →
Application:
08/659,941 →
Simplified Masking Process for Programmable Logic Device Manufacture
Patent:
5,830,795 →
Application:
08/664,190 →
A Clock Signal Providing Circuit with Enable and a Pulse Generator with Enable for Use in a Block Clock Circuit of a Programmable Logic Device
Patent:
5,760,609 →
Application:
08/666,193 →
Reference for Cmos Memory Cell Having Pmos and Nmos Transistors with a Common Floating Gate
Patent:
5,796,295 →
Application:
08/668,141 →
Programmable Logic Device with Multi-Level Power Control
Patent:
5,751,164 →
Application:
08/668,896 →
Temperature Insensitive Current Source
Patent:
5,818,294 →
Application:
08/683,373 →
Programmable Logic Device Having a Sense Amplifier with Virtual Ground
Patent:
5,734,275 →
Application:
08/683,685 →
An Integrated Circuit Having, and Process Providing, Different Oxide Layer Thicknesses on a Substrate
Patent:
5,942,780 →
Application:
08/689,523 →
Depletion Mode Pass Gates with Controlling Decoder and Negative Power Supply for a Programmable Logic Device
Patent:
5,801,551 →
Application:
08/690,768 →
Method for Programming a Programmable Logic Device in an Automatic Tester
Patent:
5,796,750 →
Application:
08/696,444 →
Oxide Formation Process for Manufacturing Programmable Logic Device
Patent:
5,960,274 →
Application:
08/699,401 →
Programmable Logic Device (Pld) Having Direct Connections Between Configurable Logic Blocks (Clbs) and Configurable Input/Output Blocks (Iobs)
Patent:
5,740,069 →
Application:
08/700,616 →
Decoder Circuit with Short Channel Depletion Transistors
Patent:
5,959,336 →
Application:
08/702,846 →
Configuration Pin Emulation Circuit for a Field Programmable Gate Array
Patent:
5,862,365 →
Application:
08/710,445 →
Programmable High Speed Routing Switch
Patent:
5,760,605 →
Application:
08/723,082 →
A Vpp Only Scalable Eeprom Memory Cell Having Transistors with Thin Tunnel Gate Oxide
Patent:
5,761,116 →
Application:
08/726,512 →
Method for Testing Field Programmable Gate Arrays
Patent:
5,991,907 →
Application:
08/729,117 →
Method for User-Controlled I/O Switching During in-Circuit Programming of Cplds Through the Ieee 1149.1 Test Access Port
Patent:
5,805,607 →
Application:
08/734,888 →
Block Clock and Initialization Circuit for a Complex High Density Pld
Patent:
5,811,987 →
Application:
08/740,948 →
Output Buffer Incorporating Shared Intermediate Nodes
Patent:
5,717,342 →
Application:
08/745,410 →
Fpga-Based Processor
Patent:
5,892,962 →
Application:
08/748,041 →
Timed Circuit Simulation in Hardware Using Fpga's
Patent:
6,028,993 →
Application:
08/781,882 →
Method of Charging and Discharging Floating Gate Transistors to Reduce Leakage Current
Patent:
5,841,701 →
Application:
08/785,096 →
Method and Apparatus Incorporating Nitrogen Selectively for Differential Oxide Growth
Patent:
5,904,575 →
Application:
08/799,153 →
Method to Incorporate, and a Device Having, Oxide Enhancement Dopants Using Gas Immersion Laser Doping (Gild) for Selectively Growing an Oxide Layer
Patent:
5,885,904 →
Application:
08/799,235 →
System and Method for Driving Columns of an Active Matrix Display
Patent:
6,157,360 →
Application:
08/815,486 →
Process for Fabricating Semiconductor Memory Device with High Data Retention Including Silicon Nitride Etch Stop Layer Formed at High Temperature with Low Hydrogen Ion Concentration
Patent:
6,190,966 →
Application:
08/823,953 →
Application Specific Modules in a Programmable Logic Device
Patent:
5,835,405 →
Application:
08/827,671 →
Memory Bits Used to Couple Look Up Table Inputs to Facilitate Increased Availability to Routing Resources Particularly for Variable Sized Look Up Tables for a Field Programmable Gate Array (Fpga)
Patent:
5,905,385 →
Application:
08/828,520 →
Fast Verify for Cmos Memory Cells
Patent:
5,844,912 →
Application:
08/831,372 →
In-System Programmable Interconnect Circuit
Patent:
6,034,541 →
Application:
08/838,487 →
Reduction of N-Channel Parasitic Transistor Leakage by Using Low Power/Low Pressure Phosphosilicate Glass
Patent:
6,087,275 →
Application:
08/843,150 →
Devices for Sourcing Constant Supply Current from Power Supply in System with Integrated Circuit Having Variable Supply Current Requirement
Patent:
5,949,279 →
Application:
08/856,926 →
Process for Fabricating Semiconductor Memory Device with High Data Retention Including Silicon Oxynitride Etch Stop Layer Formed at High Temperature with Low Hydrogen Ion Concentration
Patent:
5,989,957 →
Application:
08/859,761 →
Nonvolatile Memory Structure for Programmable Logic Devices
Patent:
5,978,272 →
Application:
08/871,589 →
Fpga Having Predictable Open-Drain Drive Mode
Patent:
6,028,447 →
Application:
08/899,428 →
System and Method for Interfacing Manually Controllable Input Devices to a Universal Computer Bus System
Patent:
5,991,546 →
Application:
08/906,775 →
Output Buffer for Making a 5.0 Volt Compatible Input/Output in a 2.5 Volt Semiconductor Process
Patent:
6,072,351 →
Application:
08/912,763 →
Voltage-Controlled Oscillator Resistant to Supply Voltage Noise
Patent:
5,955,929 →
Application:
08/920,336 →
Circuitry to Provide Fast Carry
Patent:
6,359,466 →
Application:
08/931,798 →
Hybrid Programmable Gate Arrays
Patent:
6,020,755 →
Application:
08/938,550 →
Data Retention of Eeprom Cell with Shallow Trench Isolation Using Thicker Liner Oxide
Patent:
5,854,114 →
Application:
08/947,888 →
Variable Grain Architecture for Fpga Integrated Circuits
Patent:
6,097,212 →
Application:
08/948,306 →
Programmable Clock Manager for a Programmable Logic Device That Can Generate at Least Two Different Output Clocks
Patent:
6,028,463 →
Application:
08/949,992 →
Field Programmable Gate Array Having a Dedicated Processor Interface
Patent:
6,216,191 →
Application:
08/950,444 →
Bi-Directional Buffers and Supplemental Logic and Interconnect Cells for Programmable Logic Devices
Patent:
5,986,471 →
Application:
08/950,446 →
Programmable Clock Manager for a Programmable Logic Device That Can Be Programmed Without Reconfiguring the Device
Patent:
6,060,902 →
Application:
08/950,448 →
Programmable Logic Device with Logic Cells Having a Flexible Input Structure
Patent:
6,049,224 →
Application:
08/950,624 →
Programmable Clock Manager for a Programmable Logic Device That Can Implement Delay-Locked Loop Functions
Patent:
6,043,677 →
Application:
08/951,128 →
Simultaneous Wired and Wireless Remote in-System Programming of Multiple Remote Systems
Method for Testing Field Programmable Gate Arrays
Patent:
6,003,150 →
Application:
08/974,799 →
Flexible Direct Connections Between Input/Output Blocks (Iobs) and Variable Grain Blocks (Vgbs) in Fpga Integrated Circuits
Patent:
5,990,702 →
Application:
08/995,612 →
Input/Output Block (Iob) Connections to Maxl Lines nor Lines and Dendrites in Fpga Integrated Circuits
Patent:
5,982,193 →
Application:
08/995,614 →
Programmable Input/Output Block (Iob) in Fpga Integrated Circuits
Patent:
6,034,544 →
Application:
08/995,615 →
Dual Port Sram Memory for Run Time Use in Fpga Integrated Circuits
Patent:
6,127,843 →
Application:
08/996,049 →
Multiple Input Zero Power and /nor Gate for Use in a Field Programmable Gate Array (Fpga)
Patent:
5,986,480 →
Application:
08/996,119 →
Symmetical, Extended and Fast Direct Connections Between Variable Grain Blocks in Fpga Integrated Circuits
Patent:
6,275,064 →
Application:
08/996,361 →
Process for Programming Plds and Embedded Non-Volatile Memories
Patent:
6,134,703 →
Application:
08/996,530 →
Programmable Control Multiplexing for Input/Output Blocks (Iobs) in Fpga Integrated Circuits
Patent:
6,107,823 →
Application:
08/997,221 →
Electrically Erasable and Reprogrammable, Nonvolatile Integrated Storage Device with in-System Programming and Verification (Ispav) Capabilities for Supporting in-System Reconfiguring of Pld's
Patent:
6,102,963 →
Application:
08/998,978 →
Dual Loop Delay-Locked Loop
Patent:
5,969,552 →
Application:
09/007,707 →
Synthesis-Friendly Fpga Architecture with Variable Length and Variable Timing Interconnect
Patent:
6,130,551 →
Application:
09/008,762 →
Virtual Logic System for Reconfigurable Hardware
Patent:
6,034,538 →
Application:
09/010,000 →
Sequential and Simultaneous Manufacturing Programming of Multiple in-System Programmable Systems Through a Data Network
Patent:
6,023,570 →
Application:
09/023,506 →
Spacer-Based Antifuse Structure for Low Capacitance and High Reliability and Method of Fabrication Thereof
Patent:
6,025,637 →
Application:
09/023,669 →
Eeprom Cell with Field-Edgeless Tunnel Window Using Shallow Trench Isolation Process
Patent:
6,093,946 →
Application:
09/026,814 →
Programmable Gate Array with Improved Interconnect Structure, Input/Output Structure and Configuable Logic Block
Patent:
6,128,770 →
Application:
09/037,095 →
Global Signal Distribution with Reduced Routing Tracks in an Fpga
Patent:
6,064,225 →
Application:
09/045,128 →
An Enhanced Method of Testing Semiconductor Devices Having Nonvolatile Elements
Patent:
5,982,683 →
Application:
09/046,404 →
Offset Voltage Calibration Dac with Reduced Sensitivity to Mismatch Errors
Patent:
6,556,154 →
Application:
09/053,251 →
Method of Testing and Diagnosing Field Programmable Gate Arrays
Patent:
6,108,806 →
Application:
09/059,552 →
Programmable Logic Device
Patent:
6,104,207 →
Application:
09/067,318 →
Internal Tristate Bus with Arbitration Logic
Patent:
6,154,050 →
Application:
09/067,320 →
Combination of Global Clock and Localized Clocks
Patent:
6,133,750 →
Application:
09/069,035 →
Non-Volatile Memory Element for Programmable Logic Applications and Operational Methods Therefor
Patent:
6,002,610 →
Application:
09/069,768 →
Package Migration for Related Programmable Logic Devices
Patent:
6,225,821 →
Application:
09/080,906 →
Programmable Logic Device
Patent:
6,255,847 →
Application:
09/083,205 →
Method and Structure for Dynamic in-System Programming
Patent:
6,304,099 →
Application:
09/083,335 →
Programmable Output Voltage Levels
Patent:
6,066,977 →
Application:
09/083,336 →
Stacked Tunneling Dielectric Technology for Improving Data Retention of Eeprom Cell
Patent:
6,087,696 →
Application:
09/086,437 →
Method and Apparatus for Testing Field Programmable Gate Arrays
Patent:
6,202,182 →
Application:
09/109,123 →
Electrostatic Discharge (Esd) Protection for a 5.0 Volt Compatible Input/Output (I/O) in a 2.5 Volt Semiconductor Process
Patent:
6,028,758 →
Application:
09/114,385 →
Electrostatic Discharge (Esd) Protection for Nmos Pull Up Transistors of a 5.0 Volt Compatible Output Buffer Using 2.5 Volt Process Transistors
Patent:
6,091,595 →
Application:
09/114,717 →
Ballast Resistors with Parallel Stacked Nmos Transistors Used to Prevent Secondary Breakdown During Esd with 2.5 Volt Process Transistors
Patent:
6,043,969 →
Application:
09/114,718 →
Signaling Voltage Range Discriminator
Patent:
6,124,732 →
Application:
09/115,683 →
Flexible Synchronous/and Asynchronous Circuits for a Very High Density Programmable Logic Device
Patent:
6,028,446 →
Application:
09/118,200 →
Data Retention of Eeprom Cell with Shallow Trench Isolation Using Thicker Liner Oxide
Patent:
6,064,105 →
Application:
09/134,174 →
High Speed Line Driver with Direct and Complementary Outputs
Patent:
6,087,854 →
Application:
09/145,793 →
Digital Video System and Methods for Providing Same
Patent:
6,380,978 →
Application:
09/167,527 →
Eeprom Cell with Self-Aligned Tunneling Window
Test Circuits for Testing Inter-Device Fpga Links Including a Shift Register Configured from Fpga Elements to Form a Shift Block Through Said Inter-Device Fpga Links
Patent:
6,347,387 →
Application:
09/169,848 →
Programmable Integrated Circuit Device with Slew Control and Skew Control
Patent:
6,229,336 →
Application:
09/186,917 →
Tileable and Compact Layout for Super Variable Grain Blocks Within Fpga Device
Patent:
6,154,051 →
Application:
09/187,689 →
Semiconductor-Oxide-Semiconductor Capacitor Formed in Integrated Circuit
Patent:
6,228,696 →
Application:
09/187,691 →
High Voltage Switch for Providing Voltages Higher Than 2.5 Volts with Transistors Made Using a 2.5 Volt Process
Patent:
6,169,432 →
Application:
09/188,778 →
Optimization of S/D Annealing to Minimize S/D Shorts in Memory Array
Patent:
6,291,327 →
Application:
09/192,094 →
Reduction of Mechanical Stress in Shallow Trench Isolation Process
Patent:
6,221,733 →
Application:
09/192,096 →
Power Converter with 2.5 Volt Semiconductor Process Components
Patent:
5,912,550 →
Application:
09/196,080 →
Enhanced I/O Control Flexibility for Generating Control Signals
Patent:
6,191,612 →
Application:
09/196,449 →
Eeprom Device Having Improved Data Retention and Operating Method
Patent:
6,009,033 →
Application:
09/198,653 →
Variable Sized Line Driving Amplifiers for Input/Output Blocks (Iobs) in Fpga Integrated Circuits
Patent:
6,218,857 →
Application:
09/198,796 →
Clock Tree Topology
Patent:
6,353,352 →
Application:
09/199,664 →
Method for Forming a Semiconductor Device Having High Reliability Passivation Overlying a Multi-Level Interconnect
Patent:
6,261,944 →
Application:
09/200,395 →
Phase Locked Loop with a Lock Detector
Patent:
6,133,769 →
Application:
09/201,081 →
Eeprom Cell with Tunneling Across Entire Separated Channels
Operational Amplifier with Cmos Transistors Made Using 2.5 Volt Process Transistors
Patent:
6,175,266 →
Application:
09/207,558 →
Efficient Interconnect Network for Use in Fpga Device Having Variable Grain Architecture
Patent:
6,163,168 →
Application:
09/208,203 →
Methods for Configuring Fpga's Having Variable Grain Components for Providing Time-Shared Access to Interconnect Resources
Patent:
6,124,730 →
Application:
09/212,022 →
Methods for Configuring Fpga's Having Variable Grain Blocks and Logic for Providing Time-Shared Access to Interconnect Resources
Patent:
6,100,715 →
Application:
09/212,330 →
Fpga Integrated Circuit Having Embedded Sram Memory Blocks Each with Statically and Dynamically Controllable Read Mode
Patent:
6,081,473 →
Application:
09/212,331 →
Method of Forming a Non-Volatile Memory Device
Patent:
6,214,666 →
Application:
09/216,051 →
Methods for Configuring Fpga's Having Variable Grain Blocks and Shared Logic for Providing Symmetric Routing of Result Output to Differently-Directed and Tristateable Interconnect Resources
Patent:
6,204,686 →
Application:
09/216,662 →
Method of Fabricating Programming and Erasing a Dual Pocket Two Sided Program/Erase Non-Volatile Memory Cell
Patent:
6,282,123 →
Application:
09/217,646 →
Eeprom Cell Using P-Well for Tunneling Across a Channel
Patent:
5,969,992 →
Application:
09/217,647 →
Floating Gate Memory Cell Structure with Programming Mechanism Outside the Read Path
Patent:
6,232,631 →
Application:
09/217,648 →
Eeprom Cell with Tunneling at Separate Edge and Channel Regions
Patent:
6,294,810 →
Application:
09/218,987 →
Avalanche Programmed Floating Gate Memory Cell Structure with Program Element in First Polysilicon Layer
Patent:
6,157,568 →
Application:
09/220,469 →
Avalanche Programmed Floating Gate Memory Cell Structure with Program Element in Polysilicon
Patent:
6,294,809 →
Application:
09/221,360 →
Method and Apparatus for Providing Deterministic Resets for Clock Divider Systems
Patent:
6,473,476 →
Application:
09/226,381 →
Pmos Avalanche Programmed Floating Gate Memory Cell Structure
Patent:
6,215,700 →
Application:
09/226,702 →
Methods and Apparatus for Variable Length Sdram Transfers
Patent:
6,219,747 →
Application:
09/226,776 →
Methods and Apparatus for Data Bus Arbitration
Patent:
6,393,505 →
Application:
09/227,502 →
Oxide Formation Process for Manufacturing Programmable Logic Device
Patent:
6,197,638 →
Application:
09/227,981 →
Fpga Integrated Circuit Having Embedded Sram Memory Blocks and Interconnect Channel for Broadcasting Address and Control Signals
Patent:
6,181,163 →
Application:
09/235,351 →
Multi-Port Sram Cell Array Having Plural Write Paths Including for Writing Through Addressable Port and Through Serial Boundary Scan
Patent:
6,097,664 →
Application:
09/235,356 →
Fpga Integrated Circuit Having Embedded Sram Memory Blocks with Registered Address and Data Input Sections
Patent:
6,211,695 →
Application:
09/235,615 →
Two Transistor Eeprom Cell Using P-Well for Tunneling Across a Channel
Patent:
5,999,449 →
Application:
09/239,072 →
Process for Manufacturing Shallow Trenches Filled with Dielectric Material Having Low Mechanical Stress
Patent:
6,297,128 →
Application:
09/240,560 →
Two Transistor Eeprom Cell
Patent:
6,294,811 →
Application:
09/245,813 →
Process for Fabricating a High-Endurance Non-Volatile Memory Device
Patent:
6,255,169 →
Application:
09/255,053 →
Method for Sorting Semiconductor Devices Having a Plurality of Non-Volatile Memory Cells
Patent:
6,075,724 →
Application:
09/255,410 →
Fabrication of Oxide Regions Having Multiple Thicknesses Using Minimized Number of Thermal Cycles
Patent:
6,133,164 →
Application:
09/256,245 →
Fault Tolerant Operation of Field Programmable Gate Arrays
Patent:
6,256,758 →
Application:
09/261,776 →
Semiconductor Device Having a Multi-Layer Metal Interconnect Structure
Patent:
6,075,293 →
Application:
09/263,412 →
Non-Volatile Memory Device Having a High-Reliability Composite Insulaton Layer
Patent:
6,207,989 →
Application:
09/268,897 →
High Voltage Detector to Control a Power Supply Voltage Pump for a 2.5 Volt Semiconductor Process Device
Patent:
6,163,175 →
Application:
09/276,990 →
Band Gap Reference Using a Low Voltage Power Supply
Patent:
6,031,365 →
Application:
09/276,991 →
Avalanche Injection Eeprom Memory Cell with P-Type Control Gate
Patent:
6,326,663 →
Application:
09/277,441 →
Boron Doped Silicon Capacitor Plate
Patent:
6,172,392 →
Application:
09/280,887 →
Angled Nitrogen Ion Implantation for Minimizing Mechanical Stress on Side Walls of an Isolation Trench
Patent:
6,284,626 →
Application:
09/286,830 →
High Dielectric Gate Insulator Process for Nanometer Mosfets
High Speed Logical or Circuit
Patent:
6,265,900 →
Application:
09/288,062 →
Skew-Insensitive Low Voltage Differential Receiver
Patent:
6,374,361 →
Application:
09/298,369 →
Scaling Multi-Dimensional Signals Using Variable Weighting Factors
Patent:
6,259,427 →
Application:
09/298,647 →
Floating Gate Memory Apparatus and Method for Selected Programming Thereof
Patent:
6,424,000 →
Application:
09/310,071 →
Triple-Well Eeprom Cell Using P-Well for Tunneling Across a Channel
Patent:
6,274,898 →
Application:
09/316,241 →
Current-Controlled High Voltage Discharge Scheme
Patent:
6,552,595 →
Application:
09/318,570 →
Electrically Erasable Non-Volatile Memory Cell with Integrated Scram Cell to Reduce Testing Time
Patent:
6,118,693 →
Application:
09/320,389 →
Electrically Erasable Non-Volatile Memory Cell with No Power Dissipation
Patent:
6,067,252 →
Application:
09/320,392 →
Enhanced Macrocell Module for High Density Cpld Architectures
Patent:
6,150,841 →
Application:
09/326,140 →
Display Module Driving System and Digital to Analog Converter for Driving Display
Patent:
6,940,496 →
Application:
09/326,503 →
Scalable Architecture for High Density Cpld's Having Two-Level Hierarachy of Routing Resources
Patent:
6,184,713 →
Application:
09/326,940 →
Finite State Machine with Associated Memory
Patent:
6,628,660 →
Application:
09/330,753 →
Zero-Power Cmos Non Volatile Memory Cell Having an Avalanche Injection Element
Patent:
6,028,789 →
Application:
09/334,051 →
Non-Volatile Memory Cell Having Dual Avalanche Injection Elements
Patent:
6,034,893 →
Application:
09/334,052 →
Method and Apparatus for Reducing on-Chip Memory in Vertical Video Processing
Patent:
6,587,158 →
Application:
09/359,530 →
Method and Apparatus for Efficient Video Scaling
Patent:
6,681,059 →
Application:
09/363,312 →
Method and Apparatus for Deinterlacing Digital Video Images
Patent:
6,489,998 →
Application:
09/372,713 →
Bi-Directional Data Transfer Using the Video Blanking Period in a Digital Data Stream
Patent:
6,564,269 →
Application:
09/392,229 →
Bi-Directional Data Transfer Using Two Pair of Differential Lines as a Single Additional Differential Pair
Patent:
6,307,543 →
Application:
09/393,234 →
Method and Apparatus for Bidirectional Data Transfer Between a Digital Display and a Computer
Patent:
6,738,417 →
Application:
09/393,849 →
Method and Apparatus for Detecting and Smoothing Diagonal Features Video Images
Patent:
6,515,706 →
Application:
09/396,993 →
Integrated Circuit with Standard Cell Logic and Spare Gates
Patent:
6,404,226 →
Application:
09/400,029 →
On-Line Testing of the Programmable Logic Blocks in Field Programmable Gate Arrays
Patent:
6,550,030 →
Application:
09/405,958 →
On-Line Testing of the Programmable Interconnect Network in Field Programmable Gate Arrays
Patent:
6,574,761 →
Application:
09/406,219 →
Method and Apparatus for Detecting the Source Format of Video Images
Combination of Global Clock and Localized Clocks
Patent:
6,191,609 →
Application:
09/433,642 →
Method for Minimizing Instantaneous Currents When Driving Bus Signals
Patent:
6,278,311 →
Application:
09/440,207 →
Programmable Logic Device
Patent:
6,294,925 →
Application:
09/440,460 →
Method of Operating Eeprom Memory Cells Having Transistors with Thin Gate Oxide and Reduced Disturb
Patent:
6,208,559 →
Application:
09/441,220 →
Method for in-System Programming of Serially Configured Eeproms Using a Jtag Interface of a Field Programmable Gate Array
Patent:
6,137,738 →
Application:
09/452,017 →
Inversion of Product Term Line Before or Logic in a Programmable Logic Device (Pld)
Patent:
6,326,808 →
Application:
09/454,322 →
Variable Grain Architecture for Fpga Integrated Circuits
Patent:
6,150,842 →
Application:
09/472,645 →
Audio Signal Delay Apparatus and Method
Patent:
7,203,557 →
Application:
09/478,122 →
Amplifier having an adjust resistor network
Patent:
6,362,684 →
Application:
09/506,180 →
Integrated Programmable Continuous Time Filter with Programmable Capacitor Arrays
Patent:
6,424,209 →
Application:
09/507,580 →
Output buffer for making a high voltage (5.0 volt) compatible input/output in a low voltage (2.5volt)semiconductor process
Patent:
6,351,157 →
Application:
09/548,171 →
Decoded generic routing pool
Patent:
6,288,937 →
Application:
09/567,898 →
Wide frequency-range delay-locked loop circuit
Patent:
6,326,826 →
Application:
09/574,571 →
Complementary Avalanche Injection Eeprom Cell
Patent:
6,570,212 →
Application:
09/578,086 →
Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources
Patent:
6,292,930 →
Application:
09/603,119 →
An Fpga Device and Method That Includes a Variable Grain Function Architecture for Implementing Configuration Logic Blocks and a Complimentary Variable Length Interconnect Architecture for Providing Configurable Routing Between Configuration Logic Blocks
Patent:
6,216,257 →
Application:
09/603,807 →
On-Line Fault Tolerant Operation via Incremental Reconfiguration of Field Programmable Gate Arrays
Patent:
6,530,049 →
Application:
09/611,449 →
Variable Grain Architecture for Fpga Integrated Circuits
Patent:
6,380,759 →
Application:
09/626,094 →
Configurable Logic Array Incuding Lookup Table Means for Generating Functions of Different Numbers of Input Terms
Patent:
6,567,969 →
Application:
09/632,319 →
Compact Single-Poly Two-Transistor Eeprom Cell
Patent:
6,627,947 →
Application:
09/643,279 →
High Speed Schmitt Trigger with Low Supply Voltage
Patent:
6,433,602 →
Application:
09/651,689 →
Process for Manufacturing Shallow Trenches Filled with Dielectric Material Having Low Mechanical Stress
Patent:
6,455,912 →
Application:
09/651,805 →
High voltage CMOS switch
Patent:
6,370,071 →
Application:
09/660,707 →
Programmable Logic Device
Patent:
6,462,576 →
Application:
09/661,585 →
Double Differential Comparator and Programmable Analog Block Architecture Using Same
Patent:
6,701,340 →
Application:
09/668,896 →
Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources
Patent:
6,249,144 →
Application:
09/669,186 →
On-Line Testing of Field Programmable Gate Array Resources
Patent:
6,631,487 →
Application:
09/671,853 →
Cyclic phase signal generation from a single clock source using current phase interpolation
Patent:
6,380,783 →
Application:
09/688,536 →
Scalable and Parallel Processing Methods and Structures for Testing Configurable Interconnect Network in Fpga Device
Patent:
6,470,485 →
Application:
09/692,694 →
Wide Input Programmable Logic System and Method
Patent:
6,507,212 →
Application:
09/704,487 →
Method and structure dynamic in-system programming
Patent:
6,356,107 →
Application:
09/712,000 →
Scalable architecture for high density cPLD's having two-level hierarchy of routing resources
Patent:
6,348,813 →
Application:
09/721,153 →
Combination of Bpteos Oxide Film with Cmp and Rta to Achieve Good Data Retention
Method for Forming a Semiconductor Device Using Lpcvd Nitride to Protect Floating Gate from Charge Loss
Patent:
6,287,916 →
Application:
09/731,185 →
Programmable Power Management System and Method
Methods for Configuring Fpga's Having Variable Grain Blocks and Shared Logic for Providing Symmetric Routing of Result Output to Differently-Directed and Tristateable Interconnect Resources
Baud-Rate Timing Recovery
Voltage Level Translator Systems and Methods
Sense Amplifier Systems and Methods
Patent:
6,414,521 →
Application:
09/775,489 →
Methods and Apparatus for Variable Length Sdram Transfers
Programming Programmable Logic Devices Using Hidden Switches
Method, System and Article of Manufacture for Identifying the Source Type and Quality Level of a Video Sequence
Methods for Configuring Fpga ' S Having Variable Grain Components for Providing Time-Shared Access to Interconnect Resources
Fully Differential Continuous-Time Current-Mode High Speed Cmos Comparator
Clock Signal Selection System, Method of Generating a Clock Signal and Programmable Clock Manager Including Same
Signal Distribution Scheme in Field Programmable Gate Array (Fpga) or Field Programmable System Chip (Fpsc) Including Cycle Stealing Units
Multi-Master Multi-Slave System Bus in a Field Programmable Gate Array (Fpga)
Double Data Rate Input and Output in a Programmable Logic Device
Multi-Functional I/O Buffers in a Field Programmable Gate Array (Fpga)
Field Programmable Gate Array (Fpga) Bit Stream Format
Eeprom Tunnel Window for Program Injection via P+ Contacted Inversion
Patent:
6,455,375 →
Application:
09/870,541 →
Low Jitter Integrated Phase Locked Loop with Broad Tuning Range
Patent:
6,498,538 →
Application:
09/870,877 →
Methods and Systems for Sending Side-Channel Data During Data Inactive Period
Patent:
6,954,491 →
Application:
09/881,271 →
Low Voltage, High Speed Cmos Cml Latch and Mux Devices
Patent:
6,614,291 →
Application:
09/881,950 →
High Speed Data Sampling with Reduced Metastability
Patent:
6,429,692 →
Application:
09/885,243 →
Method of Testing Serial Interface
Patent:
6,625,560 →
Application:
09/904,783 →
Clock Jitter Limiting Scheme in Video Transmission Through Multiple Stages
Patent:
7,123,307 →
Application:
09/905,318 →
Method and Apparatus for Adaptive Control of Pll Loop Bandwidth
Patent:
7,062,004 →
Application:
09/905,511 →
System and Method for Measuring Pseudo Pixel Error Rate
Patent:
6,944,804 →
Application:
09/905,615 →
Digital Display Jitter Correction Apparatus and Method
Coupling for Lc-Based Vco
Patent:
6,492,877 →
Application:
09/927,289 →
Buffering for Lc-Based Stage
Patent:
6,525,617 →
Application:
09/927,612 →
Enhanced Macrocell Module Having Expandable Product Term Sharing Capability for Use in High Density Cpld Architectures
Low Voltage Bandgap Reference Circuit
Patent:
6,489,835 →
Application:
09/941,454 →
Interlace Motion Artifact Detection Using Vertical Frequency Detection and Analysis
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
Patent:
7,131,004 →
Application:
09/945,278 →
Bi-Directional Data Transfer Using Two Pair of Differential Lines as a Single Additional Differential Pair
Method to Improve the Reliability of Thermosonic Gold to Aluminum Wire Bonds
Method and Apparatus for Sending Auxiliary Data on a Tmds-Like Link
Patent:
7,558,326 →
Application:
09/954,663 →
Multiple Width Random Number Generation
Patent:
6,832,231 →
Application:
09/966,967 →
Differential Amplifiers Using Asymmetric Transfer Characteristics to Suppress Input Noise in Output Logic Signals
Patent:
6,985,005 →
Application:
09/989,487 →
Bidirectional Bridge Circuit Having High Common Mode Rejection and High Input Sensitivity
Patent:
7,103,013 →
Application:
09/989,580 →
Multi-Phase Voltage Controlled Oscillator (Vco) with Common Mode Control
Patent:
6,717,478 →
Application:
09/989,587 →
High-Speed Bus with Embedded Clock Signals
Patent:
6,845,461 →
Application:
09/989,590 →
System and Method for Multiple-Phase Clock Generation
Patent:
6,809,567 →
Application:
09/989,645 →
Logic Gates Including Diode-Connected Metal-Oxide-Semiconductor Field-Effect Transistors (Mosfets) to Control Input Threshold Voltage Levels and Switching Transients of Output Logic Signals
Patent:
7,058,121 →
Application:
09/989,647 →
Method and System for Encrypting and Decrypting Data Using an External Agent
Patent:
7,242,766 →
Application:
09/991,057 →
Zero-Power Programmable Memory Cell
Patent:
6,611,463 →
Application:
09/991,245 →
Zero-Power Logic Cell for Use in Programmable Logic Devices
Patent:
6,489,806 →
Application:
09/992,493 →
Digital Phase Locked Loop with Programmable Digital Filter
Patent:
6,993,108 →
Application:
10/006,516 →
Digital Phase Locked Loop with Phase Selector Having Minimized Number of Phase Interpolators
Patent:
7,003,066 →
Application:
10/006,559 →
Clock Data Recovery Deserializer with Programmable Sync Detect Logic
Patent:
6,999,543 →
Application:
10/006,610 →
Non-Volatile Memory Cell with Enhanced Cell Drive Current
Patent:
6,515,899 →
Application:
10/010,011 →
Single-Poly Two-Transistor Eeprom Cell with Differentially Doped Floating Gate
Patent:
6,693,830 →
Application:
10/011,549 →
Method and System for Spatial-Temporal Dithering for Displays with Overlapping Pixels
Patent:
6,714,206 →
Application:
10/016,247 →
Programmable Input/Output Cell with Bidirectional and Shift Register Capabilities
Patent:
6,674,303 →
Application:
10/017,725 →
Structure and Method for Implementing Wide Multiplexers
Patent:
6,605,959 →
Application:
10/017,859 →
I/O Block for a Programmable Interconnect Circuit
Patent:
6,703,860 →
Application:
10/021,844 →
Programmable Interconnect Circuit with a Phase-Locked Loop
Patent:
6,661,254 →
Application:
10/021,873 →
Block-Oriented Architecture for a Programmable Interconnect Circuit
Patent:
7,154,298 →
Application:
10/022,464 →
Multi-Level Routing Structure for a Programmable Interconnect Circuit
Patent:
6,653,861 →
Application:
10/023,053 →
High Speed Interface for a Programmable Interconnect Circuit
Digital Video System and Methods for Providing Same
Method and System for Nesting of Communications Packets
Encoding Method and System for Reducing Inter-Symbol Interference Effects in Transmission Over a Serial Link
Method and System for Host Handling of Communications Errors
Memory Architecture with Multiple Serial Communications Ports
Method and System for Transition-Controlled Selective Block Inversion Communications
Method and System for Dc-Balancing at the Physical Layer
Patent:
6,771,192 →
Application:
10/045,600 →
Multisection Memory Bank System
Method and System for Integrating Packet Type Information with Synchronization Symbols
Supporting Circuitry and Method for Controlling Pixels
Patent:
7,109,958 →
Application:
10/047,772 →
Test structure for determining a minimum tunnel opening size in a non-volatile memory
Method and System for Communicating Control Information via Out-of-Band Symbols
Deinterlacing of Video Sources via Image Feature Edge Detection
Patent:
7,023,487 →
Application:
10/057,823 →
Non-Volatile Memory Element Having a Cascoded Transistor Scheme to Reduce Oxide Field Stress
Method of Preventing High Icc at Start-Up in Zero-Power Eeprom Cells for Pld Applications
Symmetrical Cml Logic Gate System
Patent:
6,680,625 →
Application:
10/066,031 →
Integrated Circuit Base Transistor Structure and Associated Programmable Cell Library
Eeprom with a Neutralized Doping at Tunnel Window Edge
Patent:
6,600,188 →
Application:
10/083,728 →
Method and System for Temporary Interruption of Video Data Transmission
Patent:
7,035,290 →
Application:
10/085,177 →
Variable Grain Architecture for Fpga Integrated Circuits
Method and System for Reducing Inter-Symbol Interference Effects in Transmission Over a Serial Link with Mapping of Each Word in a Cluster of Received Words to a Single Transmitted Word
Combining a Clock Signal and a Data Signal
Integrated Delay Discriminator for Use with a Field-Programmable Gate Array and a Method of Determining a Time Delay Thereof
Patent:
6,795,959 →
Application:
10/103,100 →
Fft Address Generation Method and Apparatus
Patent:
6,907,439 →
Application:
10/106,509 →
Skipped Carry Incrementer for Fft Address Generation
Patent:
6,976,047 →
Application:
10/108,401 →
Differential Input Comparator
Patent:
6,639,431 →
Application:
10/112,370 →
Zero Power Memory Cell with Improved Data Retention
Patent:
6,660,579 →
Application:
10/128,943 →
Polynomial Expander for Generating Coefficients of a Polynomial from Roots of the Polynomial
Patent:
7,032,162 →
Application:
10/131,883 →
Device and Method with Generic Logic Blocks
Cryptosystems Using Commuting Pairs in a Monoid
Patent:
7,136,484 →
Application:
10/133,813 →
Integrated Circuit and Associated Design Method with Antenna Error Control Using Spare Gates
Integrated Circuit and Associated Design Method Using Spare Gate Islands
Band Gap Reference Circuit
Patent:
6,720,755 →
Application:
10/146,734 →
Input Buffer with Selectable Pcl, Gtl, or Pecl Compatibility
Patent:
6,714,048 →
Application:
10/146,739 →
Input Buffer with Cmos Driver Gate Current Control Enabling Selectable Pcl, Gtl, or Pecl Compatibility
Patent:
6,870,391 →
Application:
10/146,769 →
Output Buffer with Feedback from an Input Buffer to Provide Selectable Pcl, Gtl or Pecl Compatibility
Patent:
6,657,458 →
Application:
10/146,826 →
Electrostatic Discharge Protection Circuit
Patent:
6,760,209 →
Application:
10/147,011 →
Output Buffer Having Programmable Drive Current and Output Voltage Limits
Patent:
6,714,043 →
Application:
10/147,199 →
Method of Assigning Logic Functions to Macrocells in a Programmable Logic Device
Patent:
6,848,095 →
Application:
10/150,410 →
Output Buffer with Overvoltage Protection
Patent:
6,798,244 →
Application:
10/151,753 →
Highly Linear Programmable Transconductor with Large Input-Signal Range
Patent:
6,583,652 →
Application:
10/159,009 →
Precision Analog Level Shifter with Programmable Options
Patent:
6,717,451 →
Application:
10/159,089 →
Multimode Output Stage Converting Differential to Single-Ended Signals Using Current-Mode Input Signals
Patent:
6,806,771 →
Application:
10/159,681 →
Eeprom Device with Improved Capacitive Coupling and Fabrication Process
Patent:
6,794,236 →
Application:
10/160,855 →
Eeprom Device Having a Retrograde Program Junction Region and Process for Fabricating the Device
Patent:
6,716,705 →
Application:
10/161,283 →
Method and Apparatus for Connecting Serial Ata Storage Components
Patent:
6,843,674 →
Application:
10/162,046 →
Shallow Junction Eeprom Device and Process for Fabricating the Device
Patent:
6,596,587 →
Application:
10/162,337 →
Semiconductor Device Having Metallized Interconnect Structure and Method of Fabrication
Patent:
6,703,305 →
Application:
10/164,484 →
Method and Apparatus for a Two-Wire Serial Command Bus Interface
Patent:
7,225,282 →
Application:
10/171,820 →
Method and Apparatus for Regenerating a Clock for Auxiliary Data Transmitted Over a Serial Link with Video Data
Patent:
7,088,398 →
Application:
10/171,860 →
Converting Bits to Vectors in a Programmable Logic Device
Method and Apparatus for Detecting and Smoothing Diagonal Features in Video Images
Field Programmable Gate Array Based Upon Transistor Gate Oxide Breakdown
Patent:
6,650,143 →
Application:
10/191,888 →
Method and System for Video and Auxiliary Data Transmission Over a Serial Link
Patent:
6,914,637 →
Application:
10/192,296 →
Fpga with Register-Intensive Architecture
Patent:
7,028,281 →
Application:
10/194,771 →
Integrated Programmable Continuous Time Filter with Programmable Capacitor Arrays
Memory Cell
Patent:
6,683,477 →
Application:
10/207,292 →
Crc Calculation System and Method for a Packet Arriving on an N-Byte Wide Bus
Method and System for Arbitrating Priority Bids Sent Over Serial Links to a Multi-Port Storage Device
Patent:
7,171,525 →
Application:
10/210,839 →
Eeprom Tunnel Window for Program Injection via P+ Contacted Inversion
Patent:
6,545,313 →
Application:
10/211,125 →
Dynamically Biased Full-Swing Operation Amplifier for an Active Matrix Liquid Crystal Display Driver
Patent:
6,717,468 →
Application:
10/215,936 →
Enhanced Cpld Macrocell Module Having Selectable Bypass of Steering-Based Resource Allocation and Methods of Use
Patent:
6,650,142 →
Application:
10/219,046 →
System and Method for an Adaptive State Machine to Control Signal Filtering in a Serial Link
Patent:
7,218,737 →
Application:
10/224,995 →
Eeprom Device Having an Isolation-Bounded Tunnel Capacitor and Fabrication Process
Patent:
6,841,447 →
Application:
10/232,912 →
Performing Conditional Operations in a Programmable Logic Device
Patent:
7,043,511 →
Application:
10/233,021 →
Scalable and Parallel Processing Methods and Structures for Testing Configurable Interconnect Network in Fpga Device
Patent:
6,725,442 →
Application:
10/235,380 →
Device Having Electically Isolated Low Voltage and High Voltage Regions and Process for Fabricating the Device
Patent:
6,833,602 →
Application:
10/236,114 →
Eeprom Device Having Improved Data Retention and Process for Fabricating the Device
Patent:
6,649,514 →
Application:
10/236,718 →
Eeprom Cell Having a Floating-Gate Transistor Within a Cell Well and a Process for Fabricating the Memory Cell
Patent:
6,842,372 →
Application:
10/236,829 →
Sram Cell with Single-Ended and Differential Read/Write Ports
Memory Access Circuit and Method for Reading and Writing Data with the Same Clock Signal
Patent:
6,917,536 →
Application:
10/243,014 →
Through-Board Pcb Edge Connector, System and Method
Patent:
6,814,583 →
Application:
10/244,152 →
Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer
Patent:
8,064,508 →
Application:
10/247,675 →
Eeprom Cell with Trench Coupling Capacitor
Patent:
6,700,154 →
Application:
10/251,608 →
Method and Apparatus for Deinterlacing Digital Video Images
Inkjet Printer, Drive Method and Drive Device for Same
Method of Routing in a Programmable Logic Device
Patent:
6,907,592 →
Application:
10/255,474 →
State Machine in a Programmable Logic Device
Patent:
6,803,787 →
Application:
10/255,499 →
Vector Routing in a Programmable Logic Device
Patent:
6,812,738 →
Application:
10/255,656 →
Method of Optimizing Routing in a Programmable Logic Device
Patent:
6,809,551 →
Application:
10/255,875 →
Programming Programmable Logic Devices Using Hidden Switches
Patent:
6,748,575 →
Application:
10/263,251 →
Voltage Limited Eeprom Device and Process for Fabricating the Device
Patent:
6,846,714 →
Application:
10/263,507 →
Low Voltage Differential Signaling Systems and Methods
Patent:
6,639,434 →
Application:
10/266,361 →
Cryptographic Device with Stored Key Data and Method for Using Stored Key Data to Perform an Authentication Exchange or Self Test
Patent:
7,412,053 →
Application:
10/268,832 →
Verify Scheme for a Multi-Level Routing Structure
Patent:
6,762,618 →
Application:
10/269,439 →
Power Supply Control Circuits
Expansion Method for Complex Power-Sequencing Applications
Patent:
7,111,183 →
Application:
10/269,804 →
Voltage Swing Detection Circuit for Hot Plug Event or Device Detection via a Differential Link
Patent:
7,009,827 →
Application:
10/270,882 →
Power Sequence Controller Programming Technique
Patent:
6,901,572 →
Application:
10/272,582 →
Asynchronous Glitch-Free Clock Multiplexer
Patent:
6,639,449 →
Application:
10/278,415 →
Turbo Encoder with Reduced Processing Delay
Patent:
7,051,261 →
Application:
10/282,524 →
Programmable Common Mode Termination for Input/Output Circuits
Patent:
6,700,823 →
Application:
10/283,765 →
Detection of Video Windows and Graphics Windows
Patent:
6,873,341 →
Application:
10/287,976 →
Adaptive Adjustment of Constraints During Pld Placement Processing
Placement Processing for Programmable Logic Devices
Integrated Circuit Having Self Test Capability Using Message Digest and Method for Testing Integrated Circuit Having Message Digest Generation Circuitry
Patent:
7,539,304 →
Application:
10/298,722 →
Low Jitter Integrated Phase Locked Loop with Broad Tuning Range
Patent:
6,825,733 →
Application:
10/300,190 →
Age Selection Switching Scheme for Data Traffic in a Crossbar Switch
Patent:
7,274,690 →
Application:
10/302,436 →
Flash Technology Transistors and Methods for Forming the Same
Patent:
6,797,568 →
Application:
10/302,439 →
Bandgap Reference Circuit for Improved Start-Up
Patent:
6,710,641 →
Application:
10/308,420 →
Coupling for Lc-Based Vco
Patent:
6,650,188 →
Application:
10/309,302 →
Fifo Memory Architecture
Patent:
6,777,979 →
Application:
10/334,642 →
Programmable Optimized-Distribution Logic Allocator for a High-Density Complex Pld
Patent:
6,753,696 →
Application:
10/338,619 →
Method and Circuit for Generating Time Stamp Data from an Embedded-Clock Audio Data Stream and a Video Clock
Adaptive Input Logic for Phase Adjustments
Programmable Interface Circuit for Differential and Single-Ended Signals
Noise Reduction Techniques for Programmable Input/Output Circuits
Patent:
6,812,869 →
Application:
10/367,323 →
Macrocells Supporting a Carry Cascade
Patent:
6,915,323 →
Application:
10/368,023 →
Dynamic Cross Point Switch with Shadow Memory Architecture
Patent:
6,861,870 →
Application:
10/370,232 →
Data Synchronization Across an Asynchronous Boundary Using, for Example, Multi-Phase Clocks
Bank-Based Input/Output Buffers with Multiple Reference Voltages
Patent:
6,859,066 →
Application:
10/377,320 →
Pointer Processing for Optical Communication Systems
Patent:
7,339,952 →
Application:
10/387,243 →
Automatic Lane Assignment for a Receiver
Patent:
7,305,047 →
Application:
10/387,814 →
Programmable Logic Devices with Integrated Standard-Cell Logic Blocks
Fpga Integrated Circuit Having Embedded Sram Memory Blocks with Registered Address and Data Input Sections
Patent:
39,510 →
Application:
10/392,751 →
Electronic Circuit with on-Chip Programmable Terminations
Patent:
6,967,500 →
Application:
10/397,669 →
Method and Apparatus for Controlling Signal Distribution in an Electronic Circuit
Patent:
6,873,187 →
Application:
10/400,705 →
Continuous-Time, Low-Frequency-Gain/High-Frequency-Boosting Joint Adaptation Equalizer and Method
Patent:
6,819,166 →
Application:
10/403,477 →
Hierarchical General Interconnect Architecture for High Density Fpga's
Fifo Memory with Programmable Data Port Widths
Patent:
6,986,004 →
Application:
10/409,543 →
Programmable Logic Device Architecture Based on Arrays of Lut-Based Boolean Terms
Patent:
6,879,184 →
Application:
10/417,290 →
Video/Graphics Text Mode Enhancement Method for Digitally Processed Data
Patent:
7,348,991 →
Application:
10/417,712 →
Programmable and Fixed Logic Circuitry for High-Speed Interfaces
Patent:
6,894,530 →
Application:
10/425,862 →
Scalable Device Architecture for High-Speed Interfaces
Patent:
6,903,575 →
Application:
10/425,863 →
Cascaded Logic Block Architecture for Complex Programmable Logic Devices
Patent:
6,861,871 →
Application:
10/428,885 →
Multi-Stage Interconnect Architecture for Complex Programmable Logic Devices
Patent:
6,864,713 →
Application:
10/428,888 →
Cpld with Multi-Function Blocks and Distributed Memory
Patent:
6,879,182 →
Application:
10/428,889 →
Programmable Logic Device with Enhanced Wide and Deep Logic Capability
Patent:
6,922,078 →
Application:
10/428,982 →
Method for Switching Data in a Crossbar Switch
Patent:
7,519,066 →
Application:
10/434,785 →
Method and Circuit for Dc Measurement of Phase Uniformity of Multi-Phase Clocks
Patent:
7,031,858 →
Application:
10/439,446 →
Non-Volatile and Reconfigurable Programmable Logic Devices
Patent:
6,828,823 →
Application:
10/439,602 →
Measuring Propagation Delays of Programmable Logic Devices
Patent:
7,039,842 →
Application:
10/441,814 →
Skew Cancellation for Source Synchronous Clock and Data Signals
Patent:
7,301,996 →
Application:
10/447,120 →
Digitally Controlled Delay Cells
Integrated Circuit Including External Electronic Components with Low Insertion Loss
Patent:
7,304,863 →
Application:
10/457,630 →
Flexible Media Access Control Architecture
Method and System for Encapsulation of Multiple Levels of Communication Protocol Functionality Within Line Codes
Patent:
7,187,307 →
Application:
10/459,989 →
Method and Apparatus for Encoding or Decoding Data in Accordance with an Nb/(N+1)B Block Code, and Method for Determining Such a Block Code
Patent:
6,747,580 →
Application:
10/459,992 →
Synchronization of Programmable Multiplexers and Demultiplexers
Patent:
6,856,171 →
Application:
10/460,385 →
High Speed Interface for a Programmable Interconnect Circuit
Patent:
6,861,868 →
Application:
10/463,781 →
Bi-Directional Buffering for Memory Data Lines
Integrated Circuit and Associated Design Method Using Spare Gate Islands
Patent:
6,822,477 →
Application:
10/600,042 →
High-Performance Non-Volatile Memory Device and Fabrication Process
Patent:
6,977,408 →
Application:
10/610,253 →
Noise-Shielding, Switch-Controlled Load Circuitry for Oscillators and the Like
Patent:
7,132,903 →
Application:
10/613,460 →
Programmable I/O Interfaces for Fpgas and Other Plds
Patent:
6,952,115 →
Application:
10/613,462 →
Programmable Logic Device with Hardwired Microsequencer
Patent:
6,958,625 →
Application:
10/617,980 →
Scalable Serializer-Deserializer Architecture and Programmable Interface
Patent:
7,098,685 →
Application:
10/619,645 →
Programmable Logic Device with Enhanced Wide Input Product Term Cascading
Patent:
6,903,573 →
Application:
10/619,711 →
Algorithm to Increase Logic Input Width by Cascading Product Terms
Patent:
7,032,203 →
Application:
10/620,147 →
Field Programmable Gate Array Having Embedded Memory with Configurable Depth and Width
Patent:
6,919,736 →
Application:
10/620,286 →
Programmable Logic Device with a Memory-Based Finite State Machine
Patent:
6,940,309 →
Application:
10/624,965 →
Zero Power Memory Cell with Reduced Threshold Voltage
Patent:
6,737,702 →
Application:
10/626,089 →
Programmable Lock Detector and Corrector
Patent:
6,970,047 →
Application:
10/628,656 →
Programmable Signal Termination for Fpgas and the Like
Patent:
6,924,659 →
Application:
10/628,657 →
Clock Generator with Skew Control
Clock Generator
Memory Access via Serial Memory Interface
Integrated Circuit and Associated Design Method with Antenna Error Control Using Spare Gates
Patent:
6,877,667 →
Application:
10/640,804 →
Enhanced Cpld Macrocell Module Having Selectable Bypass of Steering-Based Resource Allocation
Patent:
6,838,904 →
Application:
10/640,828 →
Programmable Broadcast Initialization of Memory Blocks
Data Sampling Method and Apparatus with Alternating Edge Sampling Phase Detection for Loop Characteristic Stabilization
Patent:
7,409,031 →
Application:
10/642,259 →
Field Programmable Gate Array
Preference Programmable First-One Detector and Quadrature Based Random Grant Generator
Patent:
7,505,422 →
Application:
10/645,786 →
Method for Multicast Service in a Crossbar Switch
Patent:
7,461,167 →
Application:
10/645,787 →
Cmos Transceiver with Dual Current Path Vco
Patent:
7,551,909 →
Application:
10/651,500 →
Shared Transmission Line Communication System and Method
Patent:
6,842,037 →
Application:
10/655,686 →
Delay-Matched Asic Conversion of a Programmable Logic Device
Patent:
7,038,490 →
Application:
10/660,814 →
Detection and Repair of Mpeg-2 Chroma Upconversion Artifacts
Controlled Hysteresis Comparator with Rail-to-Rail Input
Patent:
6,970,022 →
Application:
10/665,920 →
Programmable I/O Structure for Fpgas and the Like Having Shared Circuitry
Patent:
6,943,582 →
Application:
10/671,363 →
Programmable I/O Structure for Fpgas and the Like Having Reduced Pad Capacitance
Patent:
6,943,583 →
Application:
10/671,378 →
Multiport Memory with Twisted Bitlines
Patent:
6,909,663 →
Application:
10/671,756 →
Semiconductor Device Adapted for Forming Multiple Scan Chains
Patent:
7,269,771 →
Application:
10/676,536 →
Analog-To-Digital Converters
Patent:
6,809,674 →
Application:
10/687,468 →
Lateral High-Voltage Junction Device
Clock Generation
Patent:
7,091,763 →
Application:
10/701,005 →
Programmable Logic Device with Flexible Memory Allocation and Routing
Patent:
7,088,134 →
Application:
10/704,025 →
Programmable Power Management System and Method
Patent:
7,100,058 →
Application:
10/726,972 →
Power Supply Remote Voltage Sensing
Patent:
7,187,157 →
Application:
10/728,685 →
Linear Thermoelectric Device Driver
Patent:
6,981,381 →
Application:
10/737,514 →
Method for Configuring Multiple-Output Phase-Locked Loop Frequency Synthesizer
Patent:
7,132,864 →
Application:
10/744,353 →
Video Stream Routing and Format Conversion Unit with Audio Delay
Patent:
7,400,359 →
Application:
10/753,909 →
Content Addressable Merged Queue Architecture for Switching Data
Patent:
7,352,764 →
Application:
10/762,950 →
Reduced Dead-Cycle, Adaptive Phase Tracking Method and Apparatus
Patent:
7,236,553 →
Application:
10/763,905 →
Output Stages for High Current Low Noise Bandgap Reference Circuit Implementations
Electrostatic Discharge Simulation
Cable with Circuitry for Asserting Stored Cable Data or Other Information to an External Device or User
Combination Field Programmable Gate Array Allowing Dynamic Reprogrammability and Non-Volatile Programmability Based Upon Transistor Gate Oxide Breakdown
Upgradeable and Reconfigurable Programmable Logic Device
Semiconductor Memory Device
Fast Diagonal Interleaved Parity (Dip) Calculator
Patent:
7,191,388 →
Application:
10/791,073 →
Method and Circuit for Adaptive Equalization of Multiple Signals in Response to a Control Signal Generated from One of the Equalized Signals
Timer Systems and Methods
Powering-Up a Device Having Digital and Analog Circuitry
Systems and Methods for Controlling Voltage Regulator Module Power Supplies
Sense Amplifier Systems and Methods
Table-Based Scheduler for Fifos and the Like
Patent:
7,234,030 →
Application:
10/809,180 →
Configuring Fpgas and the Like Using One or More Serial Memory Devices
Patent:
7,095,247 →
Application:
10/809,658 →
Self-Adjusting Schmitt Trigger
Patent:
7,167,032 →
Application:
10/815,403 →
Charge Pump for a Low-Voltage Wide-Tuning Range Phase-Locked Loop
Dynamic Gain Adjustment Systems and Methods for Metastability Resistance
Patent:
6,998,896 →
Application:
10/829,865 →
Low Pass Filter Systems and Methods
Patent:
6,998,906 →
Application:
10/834,528 →
Method and Apparatus for Run Length Limited Tmds-Like Encoding of Data
Patent:
6,897,793 →
Application:
10/835,301 →
High-Voltage Protection Device and Process
Patent:
7,307,319 →
Application:
10/837,086 →
Switched Capacitor Ripple-Smoothing Filter
Data Sampling Method and Apparatus Using Through-Transition Counts to Reject Worst Sampling Position
Patent:
7,991,096 →
Application:
10/842,231 →
Control Signal Generation for a Low Jitter Switched-Capacitor Frequency Synthesizer
I/O Buffer Architecture for Programmable Devices
Patent:
7,061,269 →
Application:
10/843,708 →
Current Mode Logic Buffer
Combination Field Programmable Gate Array Allowing Dynamic Reprogrammability
Multi-Port Memory Device
Multi-Port Memory Device Having Serial I/O Interface
Memory Systems and Methods
Time Base Correction and Frame Rate Conversion
Patent:
7,710,501 →
Application:
10/889,855 →
Byte Enable Logic for Memory
Data Transmission Synchronization
Process for Fabricating a Semiconductor Device Having Electrically Isolated Low Voltage and High Voltage Regions
Patent:
7,078,286 →
Application:
10/928,563 →
Testing Embedded Memory in an Integrated Circuit
Portable Dvd Player
Field Programmable Gate Arrays Using Both Volatile and Nonvolatile Memory Cell Properties and Their Control
Memory Output Data Systems and Methods with Feedback
Field Programmable Gate Array Logic Unit and Its Cluster
Programmable Logic Device Having a Configurable Dram with Transparent Refresh
Patent:
7,129,749 →
Application:
10/974,305 →
Variable Data Width Memory Systems and Methods
Patent:
7,307,912 →
Application:
10/974,453 →
Testing Embedded Memory in Integrated Circuits Such as Programmable Logic Circuit
Patent:
7,376,872 →
Application:
10/978,899 →
Low Power Asynchronous Sense Amp
Patent:
7,161,862 →
Application:
10/996,283 →
Dynamic Over-Voltage Protection Scheme for Integrated-Circuit Devices
Patent:
7,230,810 →
Application:
11/007,954 →
Programmable Current Output Buffer
Patent:
7,215,148 →
Application:
11/012,548 →
Interface Circuitry for Electrical Systems
Patent:
7,215,149 →
Application:
11/012,550 →
Initializing Memory Blocks
Patent:
7,177,221 →
Application:
11/015,265 →
Sense Amplifier Timing
Patent:
7,177,207 →
Application:
11/015,369 →
Cascadable Memory
Patent:
7,187,203 →
Application:
11/016,665 →
Self-Verification of Configuration Memory in Programmable Logic Devices
Patent:
7,257,750 →
Application:
11/036,630 →
Eeprom Device with Voltage-Limiting Charge Pump Circuit
Patent:
7,242,053 →
Application:
11/036,738 →
Serdes with Programmable I/O Architecture
Patent:
7,208,975 →
Application:
11/040,772 →
Synchronous Memory
Patent:
7,183,798 →
Application:
11/041,319 →
Synchronization of Programmable Multiplexers and Demultiplexers
Patent:
7,109,754 →
Application:
11/044,089 →
Synchronization of Programmable Multiplexers and Demultiplexers
Patent:
7,109,756 →
Application:
11/044,149 →
Clock Generator with Skew Control
Patent:
7,034,599 →
Application:
11/044,508 →
Multi-Port Memory Systems and Methods for Bit Line Coupling
Patent:
7,221,607 →
Application:
11/054,011 →
Interlace Motion Artifact Detection Using Vertical Frequency Detection and Analysis
Data Decompression
Patent:
7,382,293 →
Application:
11/054,750 →
Data Decompression
Patent:
7,589,648 →
Application:
11/054,855 →
Programmable Logic Devices with Integrated Standard-Cell Logic Blocks
Patent:
6,975,137 →
Application:
11/055,280 →
Phase Lock Loop with Coarse Control Loop Having Frequency Lock Detector and Device Including Same
Patent:
7,102,446 →
Application:
11/056,995 →
Distributed Multiple-Channel Alignment Scheme
Output Impedance Measurement Techniques
Patent:
7,057,397 →
Application:
11/070,926 →
Differential Input Receiver with Programmable Failsafe
Patent:
7,245,154 →
Application:
11/071,356 →
Detection of Unknown Symbol Rate in a Digitally Modulated Signal
Patent:
7,376,204 →
Application:
11/083,625 →
In-System Programming of Non-Jtag Device Using Spi and Jtag Interfaces of Fpga Device
Patent:
7,265,578 →
Application:
11/098,713 →
In-System Programming of a Non-Compliant Device Using Multiple Interfaces of a Pld
Patent:
7,397,274 →
Application:
11/100,718 →
Fast Processing Path Using Field Programmable Gate Array Logic Unit
Analog-To-Digital Systems and Methods
Patent:
7,630,464 →
Application:
11/109,301 →
Field Programmable Gate Array
Electronic Switch Having Extended Voltage Range
Patent:
7,400,171 →
Application:
11/121,326 →
Apparatus for Removably Securing Storage Components in an Enclosure
Programmable I/O Interfaces for Fpgas and Other Plds
Patent:
7,009,423 →
Application:
11/134,152 →
Design Features for Testing Integrated Circuits
Patent:
7,685,483 →
Application:
11/157,345 →
Decoding Systems and Methods
Patent:
7,378,879 →
Application:
11/157,349 →
Programmable Interconnect Architecture for Programmable Logic Devices
Patent:
7,256,613 →
Application:
11/165,709 →
Programmable Logic Device with a Double Data Rate Sdram Interface
Patent:
7,342,838 →
Application:
11/165,853 →
Signal Monitoring Systems and Methods
Patent:
7,519,139 →
Application:
11/185,242 →
Output Clock Phase-Alignment Circuit
Patent:
7,253,674 →
Application:
11/187,114 →
Address Decoding Systems and Methods
Receiver for Differential and Reference-Voltage Signaling with Programmable Common Mode
Patent:
7,505,752 →
Application:
11/189,067 →
Programmable Termination for Single-Ended and Differential Schemes
Patent:
7,262,630 →
Application:
11/194,356 →
Bitline Twisting Scheme for Multiport Memory
Patent:
7,414,913 →
Application:
11/194,871 →
Clock-And-Data-Recovery System Having a Multi-Phase Clock Generator for One or More Channel Circuits
Input/Output Systems and Methods
Patent:
7,411,419 →
Application:
11/200,941 →
Programmable Logic Device with Enhanced Logic Block Architecture
Patent:
7,295,035 →
Application:
11/200,983 →
Flash Memory Erase Verification Systems and Methods
Patent:
7,187,586 →
Application:
11/201,620 →
Correlator Having User-Defined Processing
Wireless Communication Device Using Adaptive Beamforming
Zero-Power Programmable Memory Cell
Patent:
40,311 →
Application:
11/206,282 →
Digital Display Jitter Correction Apparatus and Method
Circuit Layout for Improved Performance While Preserving or Improving Density
Patent:
7,301,182 →
Application:
11/226,695 →
Data Transfer Verification Systems and Methods
Patent:
7,167,405 →
Application:
11/230,087 →
Programmable Logic Device with Power-Saving Architecture
Patent:
7,376,037 →
Application:
11/235,616 →
Electrostatic Protection Systems and Methods
Configuring Fpgas and the Like Using One or More Serial Memory Devices
Patent:
7,088,132 →
Application:
11/243,255 →
Address Isolation for User-Defined Configuration Memory in Programmable Devices
Patent:
7,196,963 →
Application:
11/251,682 →
Clock Reset Address Decoder for Block Memory
Field Programmable Gate Array
Fast-Carry Arithmetic Circuit Using a Multi-Input Look-Up Table
Patent:
7,685,215 →
Application:
11/257,137 →
Pulse-Generation Circuit with Multi-Delay Block and Set-Reset Latches
Patent:
7,317,343 →
Application:
11/257,641 →
Control Signal Generation for a Low Jitter Switched-Capacitor Frequency Synthesizer
Patent:
7,212,051 →
Application:
11/260,097 →
Digital I/O Timing Control
Interface Block Architectures
Patent:
7,327,159 →
Application:
11/287,720 →
Pseudo-Dynamic Word-Line Driver
Transparent Field Reconfiguration for Programmable Logic Devices
Patent:
7,538,574 →
Application:
11/293,941 →
Temperature-Independent, Linear on-Chip Termination Resistance
Jitter Tolerant Delay-Locked Loop Circuit
Covert Channel for Conveying Supplemental Messages in a Protocol-Defined Link for a System of Storage Devices
Differential Amplifiers Using Asymmetric Transfer Characteristics to Suppress Input Noise in Output Logic Signals
Systems and Methods for Reducing Static Phase Error
Phase-Locked Loop Systems and Methods
Dynamic Over-Voltage Protection Scheme for Interface Circuitry
Patent:
7,547,995 →
Application:
11/345,713 →
Efficient Configuration of Daisy-Chained Programmable Logic Devices
Reconfiguration of Programmable Logic Devices
Patent:
7,375,549 →
Application:
11/350,436 →
Memory Cell Comprising an Otp Nonvolatile Memory Unit and a Sram Unit
Method and Apparatus for Detecting Frequency in Digital Video Images
Programmable Logic Devices with Distributed Memory and Non-Volatile Memory
Patent:
7,355,441 →
Application:
11/360,337 →
Auto Recovery from Volatile Soft Error Upsets (Seus)
Patent:
7,596,744 →
Application:
11/361,584 →
Comparator Systems and Methods
Patent:
7,446,573 →
Application:
11/361,643 →
Dynamic Phase Offset Measurement
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Programmable Logic Devices with User Non-Volatile Memory
Patent:
7,554,358 →
Application:
11/397,985 →
Programmable Logic Devices with Transparent Field Reconfiguration
Patent:
7,459,931 →
Application:
11/398,437 →
Programmable Logic Function Generator Using Non-Volatile Programmable Memory Switches
Selective Programming of Non-Volatile Memory Facilitated by Security Fuses
Patent:
7,623,378 →
Application:
11/416,881 →
Key Generation for Advanced Encryption Standard (Aes) Decryption and the Like
Clock Distribution Chip for Generating Both Zero-Delay and Non-Zero-Delay Clock Signals
Patent:
7,657,773 →
Application:
11/425,881 →
Sense Amplifier Systems and Methods
Edge Detection
Bi-Directional Bridge Circuit Having High Common Mode Rejection and High Input Sensitivity
Selective Loading of Configuration Data into Configuration Memory Cells
Patent:
7,411,417 →
Application:
11/442,186 →
Programmable Logic Device Architecture with Multiple Slice Types
Patent:
7,378,872 →
Application:
11/445,620 →
Programmable Logic Devices with Custom Identification Systems and Methods
Patent:
7,546,498 →
Application:
11/446,308 →
Flexible Memory Architectures for Programmable Logic Devices
Patent:
7,495,970 →
Application:
11/446,309 →
Logic Block Control Architectures for Programmable Logic Devices
Patent:
7,397,276 →
Application:
11/446,351 →
Dual Slice Architectures for Programmable Logic Devices
Patent:
7,385,417 →
Application:
11/446,542 →
Programmable Logic Device Providing a Serial Peripheral Interface
Patent:
7,378,873 →
Application:
11/446,548 →
Programmable Logic Device Methods and System for Providing Multi-Boot Configuration Data Support
Patent:
7,631,223 →
Application:
11/447,591 →
Programmable Logic Device and Method of Testing
Patent:
7,463,060 →
Application:
11/452,714 →
Upgradeable and Reconfigurable Programmable Logic Device
Integrated Circuits and Complementary Cmos Circuits for Frequency Dividers
Patent:
7,411,432 →
Application:
11/461,222 →
Scan-Based Testing of Devices Implementing a Test Clock Control Structure ("Tccs")
Test Clock Control Structures to Generate Configurable Test Clocks for Scan-Based Testing of Electronic Circuits Using Programmable Test Clock Controllers
Method and Systems to Align Output Signals of an Analog-to-Digital Converter
Patent:
7,348,914 →
Application:
11/477,759 →
Original Scan Line Detection
Flash Memory Array with Independently Erasable Sectors
Patent:
7,636,259 →
Application:
11/487,647 →
Negative Voltage Blocking for Embedded Memories
Patent:
7,512,015 →
Application:
11/487,751 →
Charge Pump with Four-Well Transistors
Switch Sequencing Circuit Systems and Methods
Methods and Systems for Storing a Security Key Using Programmable Fuses
Patent:
7,675,313 →
Application:
11/498,645 →
Area Efficient Routing Architectures for Programmable Logic Devices
Patent:
7,605,606 →
Application:
11/498,646 →
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
Smart scalable storage switch architecture
Source-Adaptive Video Deinterlacer
Clock Systems and Methods
Patent:
7,456,672 →
Application:
11/530,620 →
Efficient Bitstream Compression
Patent:
7,511,641 →
Application:
11/533,188 →
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
Multiple Communication Channel Configuration Systems and Methods
Patent:
7,831,754 →
Application:
11/551,459 →
Multiplexer Initialization Systems and Methods
Patent:
7,663,401 →
Application:
11/556,528 →
Programmable Logic Device Programming Verification Systems and Methods
Patent:
7,725,803 →
Application:
11/557,808 →
Method of Context Adaptive Binary Arithmetic Coding and Coding Apparatus Using the Same
Patent:
7,365,659 →
Application:
11/567,514 →
Planar Antenna
Patent:
8,022,887 →
Application:
11/588,472 →
Determining Oversampled Data to Be Included in Unit Intervals
Programmable Current Output and Common-Mode Voltage Buffer
Patent:
7,535,258 →
Application:
11/593,274 →
Data Transfer Verification Systems and Methods
Patent:
7,623,391 →
Application:
11/624,021 →
Adaptive Bandwidth Phase Locked Loop with Feedforward Divider
Low Static Current Drain Logic Circuit
Output Buffer with Digital Slew Control
Patent:
7,443,192 →
Application:
11/643,288 →
Current Mode Circuitry to Modulate a Common Mode Voltage
Concurrent Code Checker and Hardware Efficient High-Speed I/O Having Built-in Self-Test and Debug Features
Parallel Interface Bus to Communicate Video Data Encoded for Serial Data Links
High Fan-Out Signal Routing Systems and Methods
Patent:
7,576,563 →
Application:
11/671,948 →
Flash Memory Erase Verification Systems and Methods
Patent:
7,313,025 →
Application:
11/675,246 →
Diagonal Interleaved Parity Calculator
Patent:
7,430,706 →
Application:
11/676,071 →
Serdes with Programmable I/O Architecture
Patent:
7,327,160 →
Application:
11/676,196 →
Redundant Configuration Memory Systems and Methods
Circuitry to Prevent Peak Power Problems During Scan Shift
Mechanism for Streaming Media Data Over Wideband Wireless Networks
Shared Nonvolatile Memory Architecture
Progressive Power Control of a Multi-Port Memory Device
Power-Saving Clocking Technique
Logic Analyzer Systems and Methods for Programmable Logic Devices
Patent:
7,536,615 →
Application:
11/691,003 →
Logic Analyzer Systems and Methods for Programmable Logic Devices
Patent:
7,743,296 →
Application:
11/691,040 →
Multi-Port Memory Device Having Variable Port Speeds
Inter-Port Communication in a Multi-Port Memory Device
Hd Physical Layer of a Wireless Communication Device
Adaptive Beam-Steering Methods to Maximize Wireless Link Budget and Reduce Delay-Spread Using Multiple Transmit and Receive Antennas
Method and Apparatus for a Two-Wire Serial Command Bus Interface
Low Power Very High-Data Rate Device
Clock Boosting Systems and Methods
Patent:
7,509,598 →
Application:
11/737,702 →
Interface Test Circuitry and Methods
Integrated Circuit Temperature Sensor Systems and Methods
Patent:
7,632,011 →
Application:
11/750,616 →
Self-Verification of Configuration Memory in Programmable Logic Devices
Patent:
7,401,280 →
Application:
11/750,790 →
Millimeter Wave Integrated Circuit Interconnection Scheme
Application:
11/752,073 →
Publication:
US 2008/0290959
Surface Mountable Integrated Circuit Packaging Scheme
Digital Video Interface with Bi-Directional Half-Duplex Clock Channel Used as Auxiliary Data Channel
Soft Error Detection Logic Testing Systems and Methods
Patent:
8,065,574 →
Application:
11/760,411 →
Programmable Logic Device Providing Serial Peripheral Interfaces
Patent:
7,570,078 →
Application:
11/761,221 →
Distributed Front-End Fifo for Source-Synchronized Interfaces with Non-Continuous Clocks
Patent:
7,573,770 →
Application:
11/778,457 →
Compression and Decompression of Configuration Data for Programmable Logic Devices
Patent:
7,446,679 →
Application:
11/779,246 →
Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer
On Screen Displays Associated with Remote Video Source Devices
Data Stream Control for Network Devices
Streaming Data Content in a Network
Application:
11/828,226 →
Publication:
US 2009/0028142
Communications Architecture for Transmission of Data Between Memory Bank Caches and Ports
Packet Level Prioritization in Interconnection Networks
Bandwidth Reservation for Data Flows in Interconnection Networks
Network Repository for Metadata
Receiver and Transmitter Calibration to Compensate for Frequency Dependent I/Q Imbalance
Patent:
7,856,050 →
Application:
11/839,107 →
Synchronizing Related Data Streams in Interconnection Networks
Ensuring Physical Locality of Entities Sharing Data
Cable with Circuitry for Asserting Stored Cable Data or Other Information to an External Device or User
Delivering on Screen Display Data to Existing Display Devices
Parameter Scanning for Signal Over-Sampling
Signal Interleaving for Serial Clock and Data Recovery
Weight Based Look Up Table Collapsing for Programmable Logic Devices
Patent:
7,681,160 →
Application:
11/863,016 →
Variable Data Width Memory Systems and Methods
Patent:
7,539,076 →
Application:
11/865,556 →
Adaptive Equalizer for Use with Clock and Data Recovery Circuit of Serial Communication Link
Hysteresis-Based Processing for Applications Such as Signal Bias Monitors
Patent:
7,616,029 →
Application:
11/869,019 →
Dynamic Delay or Advance Adjustment of Oscillating Signal Phase
Patent:
7,586,344 →
Application:
11/872,950 →
Scan Chain Systems and Methods for Programmable Logic Devices
Patent:
7,757,198 →
Application:
11/875,748 →
Single-Ended Output Driver Buffer
Patent:
7,411,414 →
Application:
11/877,434 →
Modified Branch Metric for Decoders and Equalizers
Patent:
7,986,753 →
Application:
11/901,069 →
Channel-To-Channel Deskew Systems and Methods
Patent:
8,132,040 →
Application:
11/924,088 →
Interlace Motion Artifact Detection Using Vertical Frequency Detection and Analysis
Programmable Logic Device with Enhanced Logic Block Architecture
Patent:
7,573,291 →
Application:
11/934,711 →
Simultaneous Switching Output Noise Estimation and Reduction Systems and Methods
Patent:
7,895,555 →
Application:
11/937,300 →
Input/Output Placement Systems and Methods to Reduce Simultaneous Switching Output Noise
Patent:
7,788,620 →
Application:
11/937,328 →
Multi-Transformer Architecture for an Active Rf Circuit
Flexible Delay Cell Architecture
Patent:
7,863,931 →
Application:
11/939,787 →
Register Data Retention Systems and Methods During Reprogramming of Programmable Logic Devices
Patent:
7,535,253 →
Application:
11/941,006 →
Compression and Decompression of Configuration Data Using Repeated Data Frames
Patent:
7,902,865 →
Application:
11/941,031 →
Noise Cancellation
Composite Wire Indexing for Programmable Logic Devices
Patent:
7,788,623 →
Application:
11/947,662 →
Integrated Circuit Having Independent Voltage and Process/Temperature Control
Patent:
7,586,325 →
Application:
11/949,130 →
Interface Block Architectures
Patent:
7,427,874 →
Application:
11/949,454 →
Cryptographic Device with Stored Key Data and Method for Using Stored Key Data to Perform an Authentication Exchange or Self Test
Patent:
7,797,536 →
Application:
11/950,088 →
Bank Sharing and Refresh in a Shared Multi-Port Memory Device
Programmable Level Shifter
Patent:
7,605,609 →
Application:
11/957,598 →
Programmable Logic Device with Built in Self Test
Patent:
7,630,259 →
Application:
11/959,329 →
Method, Apparatus and System for Generating and Facilitating Mobile High-Definition Multimedia Interface
Control Bus for Connection of Electronic Devices
Discovery of Electronic Devices Utilizing a Control Bus
Process Charging Monitor for Nonvolatile Memory
Patent:
7,646,643 →
Application:
11/970,212 →
Wireless Hd Mac Frame Format
Wireless Hd Av Packet Format
Concurrent Association with Multiple Wireless Networks
Serial Interface for Programmable Logic Devices
Patent:
7,728,625 →
Application:
12/001,600 →
Wireless Proximity Estimation
Programmable Logic Device with a Multi-Data Rate Sdram Interface
Patent:
7,787,326 →
Application:
12/019,526 →
Internally Triggered Reconfiguration of Programmable Logic Devices
Patent:
8,069,329 →
Application:
12/021,202 →
Reconfiguration of Programmable Logic Devices
Patent:
7,652,500 →
Application:
12/044,842 →
Extensions to Adaptive Beam-Steering Method
Wire Mapping for Programmable Logic Devices
Patent:
7,890,913 →
Application:
12/055,170 →
Bi-Directional Digital Interface for Video and Audio (Diva)
Rf Integrated Circuit Test Methodology and System
Programmable Logic Devices with Distributed Memory
Patent:
7,459,935 →
Application:
12/060,776 →
Detection of Timing Errors in Programmable Logic Devices
Patent:
7,831,856 →
Application:
12/061,885 →
Method, Apparatus, and System for Employing an Enhanced Port Multiplier
Method, Apparatus, and System for Port Multiplier Enhancement
Security Mechanism for Wireless Video Area Networks
On-Chip Temperature Sensor for an Integrated Circuit
Patent:
7,661,878 →
Application:
12/099,933 →
Programmable Logic Device with Power-Saving Architecture
Patent:
7,558,143 →
Application:
12/100,859 →
Synchronization of Data Signals and Clock Signals for Programmable Logic Devices
Patent:
7,557,606 →
Application:
12/105,146 →
Programmable Logic Device with Multiple Slice Types
Patent:
7,696,784 →
Application:
12/105,959 →
Power Management Systems and Methods for Programmable Logic Devices
Patent:
7,560,953 →
Application:
12/107,883 →
Formation of High Voltage Transistor with High Breakdown Voltage
Patent:
7,897,448 →
Application:
12/122,489 →
Digital Signal Processing Block Architecture for Programmable Logic Device
Patent:
8,463,832 →
Application:
12/146,042 →
Operation of Media Interface to Provide Bidirectional Communications
Logic Block Control Architectures for Programmable Logic Devices
Patent:
7,592,834 →
Application:
12/164,265 →
Exchanging Information Between Components Coupled with an a I2C Bus via Separate Banks
Application:
12/164,757 →
Publication:
US 2009/0327572
Connection Control in a Wireless Communication System
Device Discovery in a Wireless Communication System
Dispatch Capability Using a Single Physical Interface
Bitmap Device Identification in a Wireless Communication System
Initializing a Transceiver in a Wireless Communication System
Wireless Architecture for 60GHZ
Methods and Mechanisms for Probabilistic Color Correction
Synchronization of Serial Data Signals
Patent:
8,261,160 →
Application:
12/182,940 →
Selective Loading of Configuration Data into Configuration Memory Cells
Patent:
7,579,865 →
Application:
12/186,027 →
Low-Power Output Driver Buffer Circuit
Patent:
7,605,602 →
Application:
12/188,120 →
Group Power Management of Network Devices
System, Method, and Apparatus for Smoothing of Edges in Images to Remove Irregularities
Mechanism for communication with multiple wireless video area networks
Application:
12/215,959 →
Publication:
US 2009/0086695
Passive Equalizer with Negative Impedance to Increase a Gain
Programmable Signal Routing Systems Having Low Static Leakage
High Speed Integrated Circuit Interface
Patent:
9,367,495 →
Application:
12/242,665 →
Method, Apparatus, and System for Automatic Data Aligner for Multiple Serial Receivers
Coding System for Memory Systems Employing High-Speed Serial Links
Clock Systems and Methods
Patent:
7,663,419 →
Application:
12/273,868 →
Transmitter and Receiver Using Asymmetric Transfer Characteristics in Differential Amplifiers to Suppress Noise
Congestion-Driven Placement Systems and Methods for Programmable Logic Devices
Patent:
8,112,731 →
Application:
12/277,217 →
Method, Apparatus and System for Employing a Content Protection System
Congestion Estimation for Programmable Logic Devices
Patent:
7,992,120 →
Application:
12/323,974 →
Programmable Logic Device and Method of Testing
Patent:
7,656,193 →
Application:
12/327,128 →
Technique for Low-Power Operation of a Wireless Device
Congestion Estimation Based on Routing Resources of Programmable Logic Devices
Patent:
8,856,718 →
Application:
12/337,502 →
Multi-Priority Placement for Configuring Programmable Logic Devices
Patent:
8,181,139 →
Application:
12/341,929 →
Method, Apparatus, and System for Pre-Authentication and Keep-Authentication of Content Protected Ports
Method and System for Detecting Successful Authentication of Multiple Ports in a Time-Based Roving Architecture
Fault Testing for Interconnections
Temperature-Independent, Linear on-Chip Termination Resistance
Patent:
7,714,608 →
Application:
12/370,039 →
Flexible Memory Architectures for Programmable Logic Devices
Patent:
7,957,208 →
Application:
12/389,149 →
Method, Apparatus, and System for Deciphering Media Content Stream
Method, Apparatus, and System for Pre-Authentication and Processing of Data Streams
Receiver for Differential and Reference Voltage Signaling with Programmable Common Mode
Patent:
7,844,243 →
Application:
12/402,751 →
Routing Signals to Pins of Components in Programmable Logic Devices
Patent:
8,069,431 →
Application:
12/406,772 →
Clock Boosting Systems and Methods
Patent:
8,086,986 →
Application:
12/408,047 →
Dual-Slice Architectures for Programmable Logic Devices
Patent:
7,675,321 →
Application:
12/409,757 →
Efficient Bitstream Compression
Patent:
7,808,405 →
Application:
12/413,787 →
Soft Error Upset Hardened Integrated Circuit Systems and Methods
Patent:
7,741,865 →
Application:
12/430,848 →
Register Data Retention Systems and Methods During Reprogramming of Programmable Logic Devices
Patent:
7,876,125 →
Application:
12/464,822 →
Reading an External Memory Device to Determine Its Interface Characteristics for Configuring a Programmable Logic Device
Patent:
7,868,654 →
Application:
12/465,444 →
Transparent Field Reconfiguration for Programmable Logic Devices
Patent:
7,737,723 →
Application:
12/467,800 →
Fpga Having Low Power, Fast Carry Chain
Programmable Logic Devices with Custom Identification Systems and Methods
Patent:
7,702,977 →
Application:
12/480,565 →
Detection of Encryption Utilizing Error Detection for Received Data
In-System Reconfigurable Circuit for Mapping Data Words of Different Lengths
Patent:
8,165,164 →
Application:
12/494,822 →
Computer Memory Test Structure
Power Management for Integrated Circuits Such as Programmable Logic Devices
Patent:
7,724,029 →
Application:
12/502,141 →
Programmable Logic Device Providing Serial Peripheral Interfaces
Patent:
7,768,300 →
Application:
12/511,388 →
Signaling for Transitions Between Modes of Data Transmission
Clock Delay and Skew Control Systems and Methods
Patent:
8,255,733 →
Application:
12/512,944 →
Oscillator Tuning for Phase-Locked Loop Circuit
Patent:
7,969,248 →
Application:
12/512,961 →
Multi-Antenna Transmitter for Multi-Tone Signaling
Distributed Front-End Fifo for Source-Synchronous Interfaces with Non-Continuous Clocks
Patent:
7,808,855 →
Application:
12/538,810 →
Current Mode Circuitry to Modulate a Common Mode Voltage
Auto Recovery from Volatile Soft Error Upsets (Seus)
Patent:
8,010,871 →
Application:
12/561,140 →
Redundant Configuration Memory Systems and Methods
Patent:
7,746,107 →
Application:
12/564,781 →
Messaging to Provide Data Link Integrity
Multi-Antenna Beam-Forming System for Transmitting Constant Envelope Signals Decomposed from a Variable Envelope Signal
Bi-Directional Bridge Circuit Having High Common Mode Rejection and High Input Sensitivity
Discovery of Connections Utilizing a Control Bus
Clock Distribution Chip
Patent:
8,122,277 →
Application:
12/578,470 →
Clock Distribution Chip
Patent:
8,112,656 →
Application:
12/578,492 →
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Transmission of Alternative Content Over Standard Device Connectors
Shallow Trench Isolation (Sti) with Trench Liner of Increased Thickness
Patent:
7,985,656 →
Application:
12/607,333 →
Shallow Trench Isolation (Sti) with Trench Liner of Increased Thickness
Patent:
7,989,911 →
Application:
12/607,868 →
Flash Memory Array with Independently Erasable Sectors
Patent:
8,059,470 →
Application:
12/611,262 →
Programmable Logic Device with Built in Self Test
Patent:
7,944,765 →
Application:
12/626,289 →
Programmable Logic Device and Methods for Providing Multi-Boot Configuration Data Support
Patent:
8,060,784 →
Application:
12/630,163 →
Power Delivery Over Digital Interaction Interface for Video and Audio (Diiva)
Combined Variable Gain Amplifier and Analog Equalizer Circuit
Patent:
8,200,179 →
Application:
12/637,884 →
Method, Apparatus, and System for Simultaneously Previewing Contents from Multiple Protected Sources
Application:
12/650,357 →
Publication:
US 2011/0157473
Antenna Array with Flexible Interconnect for a Mobile Wireless Device
Technique for Determining an Angle of Arrival in a Communication System
Communication Using Continuous-Phase Modulated Signals
Multi-Site Testing of Computer Memory Devices and Serial Io Ports
Separate Configuration of I/O Cells and Logic Core in a Programmable Logic Device
Patent:
8,040,152 →
Application:
12/698,283 →
Enhanced Wireless Data Rates Using Multiple Beams
Patent:
8,588,193 →
Application:
12/699,758 →
Enhanced Wireless Data Rates Using Multiple Beams
Patent:
8,457,026 →
Application:
12/699,781 →
Block Noise Detection and Filtering
Hybrid Interface for Serial and Parallel Communication
Latency Measurements for Wireless Communications
Patent:
7,924,054 →
Application:
12/706,227 →
Method and Devices for Storing a Security Key Using Programmable Fuses
Patent:
7,834,652 →
Application:
12/709,685 →
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Video Frame Synchronization
Comparator with Jitter Mitigation
Patent:
8,040,159 →
Application:
12/729,952 →
Transforming Signals Using Passive Circuits
Adaptive Beam-Steering Methods to Maximize Wireless Link Budget and Reduce Delay-Spread Using Multiple Transmit and Receive Antennas
Configuring Multiple Programmable Logic Devices with Serial Peripheral Interfaces
Patent:
8,384,427 →
Application:
12/752,455 →
Bondwire Configuration for Reduced Crosstalk
Patent:
8,664,774 →
Application:
12/757,087 →
Multi-Level Port Expansion for Port Multipliers
Programmable Logic Device Programming Verification Systems and Methods
Patent:
8,108,754 →
Application:
12/786,359 →
Shared-Array Multiple-Output Digital-to-Analog Converter
Patent:
8,164,499 →
Application:
12/813,540 →
Delaying Data Signals
Patent:
8,441,292 →
Application:
12/813,573 →
Mechanism for Memory Reduction in Picture-in-Picture Video Generation
Soft Error Upset Hardened Integrated Circuit Systems and Methods
Patent:
7,868,646 →
Application:
12/818,544 →
Mechanism for Internal Processing of Content Through Partial Authentication on Secondary Channel
Mechanism for Partial Encryption of Data Streams
17B/20B Coding System
Multi-View Display System
Composite Wire Indexing for Programmable Logic Devices
Patent:
8,286,116 →
Application:
12/871,764 →
De-Encapsulation of Data Streams into Multiple Links
Testing of High-Speed Input-Output Devices
Combining Video Data Streams of Differing Dimensionality for Concurrent Display
Displacement Sensing Using a Flexible Substrate
Discovery of Electronic Devices in a Combined Network
Transfer of Control Bus Signaling on Packet-Switched Network
Application:
12/950,867 →
Publication:
US 2012/0131245
Transmission and Handling of Three-Dimensional Video Content
Application:
12/966,194 →
Publication:
US 2011/0149032
Bitline Floating Circuit for Memory Power Reduction
Patent:
8,351,287 →
Application:
12/976,412 →
Triggered Sense Amplifier
Patent:
8,477,549 →
Application:
12/976,520 →
Blocking Memory Readback In A Programmable Logic Device
Patent:
8,522,126 →
Application:
12/977,011 →
Mechanism for Facilitating a Configurable Port-Type Peripheral Component Interconnect Express/Serial Advanced Technology Attachment Host Controller Architecture
Adaptive Interconnection Scheme for Multimedia Devices
Serializer with Odd Gearing Ratio
Patent:
8,274,412 →
Application:
12/987,393 →
Transmission and Detection of Multi-Channel Signals in Reduced Channel Format
Pre-Configuration Programmability of I/O Circuitry
Patent:
8,384,428 →
Application:
13/006,622 →
Programmable Buffer
Patent:
8,324,934 →
Application:
13/007,688 →
Low-Power, Glitch-Less, Configurable Delay Element
Patent:
8,248,136 →
Application:
13/007,804 →
Determination of Physical Connectivity Status of Devices Based on Electrical Measurement
Wire Mapping for Programmable Logic Devices
Patent:
8,104,009 →
Application:
13/026,555 →
Compression and Decompression of Configuration Data Using Repeated Data Frames
Patent:
8,058,898 →
Application:
13/034,174 →
Low-Voltage Current Sense Amplifier
Patent:
8,654,600 →
Application:
13/037,703 →
Programmable Logic Device Wakeup Using a General Purpose Input/Output Port
Patent:
8,368,424 →
Application:
13/038,259 →
Variable Response Mode for Synchronous Data Read
Patent:
8,816,718 →
Application:
13/038,270 →
Voltage Discharge Circuit Having Divided Discharge Current
Patent:
8,553,463 →
Application:
13/052,142 →
Safe Programming of Key Information into Non-Volatile Memory for a Programmable Logic Device
Patent:
8,319,521 →
Application:
13/076,300 →
Power Control Block with Output Glitch Protection
Patent:
8,314,634 →
Application:
13/079,578 →
Phase Locked Loop Circuit with Selectable Feedback Paths
Patent:
8,531,222 →
Application:
13/079,595 →
Adjustment of Clock Signals Regenerated from a Data Stream
Latency Measurements for Wireless Communications
Patent:
8,138,790 →
Application:
13/083,889 →
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Audio and Video Data Multiplexing for Multimedia Stream Switch
Apparatus, System, and Method for a Compact Symmetrical Transition Structure for Radio Frequency Applications
Edge Detection
Flexible Updating of Multi-Bit Registers
Patent:
8,441,284 →
Application:
13/154,885 →
Voltage Regulators with a Shared Capacitor
Patent:
8,547,075 →
Application:
13/155,547 →
Integrated Circuit Design Software with Cross Probing Between Tool Graphical User Interfaces (Guis)
Patent:
8,555,217 →
Application:
13/164,108 →
Detection of Cable Connections for Electronic Devices
Detection of Cable Connections for Electronic Devices
Mechanism for Facilitating Fine-Grained Self-Refresh Control for Dynamic Memory Devices
Configurable Multi-Dimensional Driver and Receiver
Single-Ended Configurable Multi-Mode Driver
Alignment Circuit for Parallel Data Streams
Patent:
8,495,264 →
Application:
13/178,536 →
Simultaneous Development of Complementary Ic Families
Patent:
8,539,409 →
Application:
13/178,599 →
Method and System for Placing Integrated Circuits into Predominantly Ultra-Low Voltage Mode for Standby Purposes
Patent:
8,314,632 →
Application:
13/193,984 →
Conversion of Multimedia Data Streams for Use by Connected Devices
Dual-Port Sram with Bit Line Clamping
Patent:
8,451,679 →
Application:
13/212,121 →
Conversion and Processing of Deep Color Video in a Single Clock Domain
Identification and Handling of Data Streams Using Coded Preambles
Comparator with Jitter Mitigation
Patent:
8,169,237 →
Application:
13/275,102 →
Iddq Testing of Cmos Devices
Application:
13/298,001 →
Publication:
US 2012/0158346
Testing of Soft Error Detection Logic for Programmable Logic Devices
Patent:
8,370,691 →
Application:
13/299,507 →
Multimedia I/O System Architecture for Advanced Digital Television
Ringing Suppression in Video Scalers
Application:
13/335,398 →
Publication:
US 2013/0162901
Mechanism for Clock Recovery for Streaming Content Being Communicated Over a Packetized Communication Network
Application:
13/339,339 →
Publication:
US 2012/0182473
Proxy Device Operation in Command and Control Network
Mechanism for Low Power Standby Mode Control Circuit
Surface Mountable Integrated Circuit Packaging Scheme
Application:
13/403,146 →
Programmable Logic Device Data Rate Booster for Digital Signal Processing
Patent:
8,977,885 →
Application:
13/412,408 →
Method, Apparatus and System for Transitioning an Audio/Video Device Between a Source Mode and a Sink Mode
In-System Reconfigurable Circuit for Mapping Data Words of Different Lengths
Patent:
8,823,561 →
Application:
13/452,060 →
Mechanism for Facilitating Cost-Efficient and Low-Latency Encoding of Video Streams
Application:
13/460,393 →
Publication:
US 2013/0287100
Signal Distribution Networks and Related Methods
Phase Detection Circuits and Methods
MULTI-MEDIA USB DATA TRANSFER OVER DIGITAL INTERACTION INTERFACE FOR VIDEO AND AUDIO (DiiVA)
Application:
13/521,739 →
Publication:
US 2013/0191570
Video Management and Control in Home Multimedia Network
Automated Service Discovery and Dynamic Connection Management
Transmission of Multiple Protocol Data Elements via an Interface Utilizing a Data Tunnel
Directional Beam Steering System and Method to Detect Location and Motion
Low-Power Configurable Delay Element
Patent:
8,461,894 →
Application:
13/585,142 →
Test Solution for Ring Oscillators
Combining Video and Audio Streams Utilizing Pixel Repetition Bandwidth
Serializer with Multiple Stages
Patent:
8,912,933 →
Application:
13/616,173 →
Interfacing Between Integrated Circuits with Asymmetric Voltage Swing
Triple-Trim Reference Voltage Generator
Patent:
8,710,898 →
Application:
13/653,827 →
Methods and Apparatuses to Provide an Electro-Optical Alignment
Placing Integrated Circuits into Low Voltage Mode for Standby Purposes
Patent:
8,643,398 →
Application:
13/680,947 →
Multi-Channel Transmitter Synchronization Circuitry
Patent:
9,819,478 →
Application:
13/681,782 →
Integrated Circuit Package with Input Capacitance Compensation
Patent:
8,643,168 →
Application:
13/685,385 →
Methods and Systems for Near-Field MIMO Communications
In-System Margin Measurement Circuit
Patent:
8,686,773 →
Application:
13/721,867 →
High-Accuracy Detection in Collaborative Tracking Systems
Mechanism for Facilitating Dynamic Timestamp-Less Clock Generation for Transmitting Media Streams Over Shared Channels
Hybrid H-Bridge and Cml Driver
Patent:
8,797,064 →
Application:
13/738,265 →
Method and Apparatus for Reducing Digital Video Image Data
Application:
13/738,768 →
Publication:
US 2014/0152891
Communication Bridging Between Devices via Multiple Bridge Elements
Programmable Signal Routing Systems Having Low Static Leakage
Patent:
45,200 →
Application:
13/764,221 →
Configurable Single-Ended Driver
Transmitting Multiple Differential Signals Over a Reduced Number of Physical Channels
Computer Memory Test Structure
Apparatus, System and Method for Providing Clock and Data Signaling
Leakage-Current Abatement Circuitry for Memory Arrays
Integrated Connector/Flex Cable
Auxiliary Data Encoding in Video Data
Application:
13/787,664 →
Publication:
US 2014/0204994
Mechanism for Facilitating Synchronization of Audio and Video Between Multiple Media Devices
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Integration of Signal Sampling Within Transistor Amplifier Stage
Full-Frame Buffer to Improve Video Performance in Low-Latency Video Communication Systems
Electronic Alignment of Optical Signals
Application:
13/844,152 →
Publication:
US 2014/0193165
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Integrated Circuit with Pin for Setting Digital Address
Patent:
8,786,482 →
Application:
13/857,919 →
Highly Secure and Extensive Scan Testing of Integrated Circuits
Antenna Selection and Pilot Compression in Mimo Systems
Loss of Signal Detection for High-Speed Serial Links
Method, Apparatus and System for Communicating Sideband Data with Non-Compressed Video
Patent:
8,786,776 →
Application:
13/891,842 →
Delaying Data Signals
Block Noise Detection and Filtering
Dual-Port Sram with Bit Line Clamping
Configuration Sequence for Programmable Logic Device
Multiple Protocol Tunneling Using Time Division Operations
Network Repository for Metadata
Hybrid Interface for Serial and Parallel Communication
Integrated Mobile Desktop
Stable Supply-Side Reference Over Extended Voltage Range With Hot-Plugging Compatibility
Discovery of Electronic Devices in a Combined Network
Elements to Counter Transmitter Circuit Performance Limitations
Integrated Phase-Shifting-and-Combining Circuitry to Support Multiple Antennas
Tracking System with Orthogonal Polarizations and a Retro-Directive Array
Phase Locked Loop Circuit with Selectable Feedback Paths
Application:
14/021,513 →
Publication:
US 2014/0009194
Multi-Site Testing of Computer Memory Devices and Serial Io Ports
Dynamic Power Supply Switching for Clocking Signals
Patent:
8,829,944 →
Application:
14/040,955 →
Serdes Interface Architecture for Multi-Processor Systems
Configuration of Selected Modules of a Hardware Block Within a Programmable Logic Device
System, Method, and Apparatus for Smoothing of Edges in Images to Remove Irregularities
Multi-Antenna Transmitter for Multi-Tone Signaling
Smart Scalable Storage Switch Architecture
On Screen Displays Associated with Remote Video Source Devices
Partially Depopulated Interconnection Arrays for Packaged Semiconductor Devices and Printed Circuit Boards
Signal Distribution Networks and Related Methods
Multi-View Display System
Esd Protection Using Shared Rc Trigger
Communication Using Continuous-Phase Modulated Signals
Mechanism for Facilitating Dynamic Phase Detection with High Jitter Tolerance for Images of Media Streams
Compensation Scheme for Mhl Common Mode Clock Swing
Line Driver with Separate Pre-Driver for Feed-Through Capacitance
Driving Data of Multiple Protocols Through a Single Set of Pins
Formatting Audio-Video Information Compliant with First Transmission Format to Second Transmission Format in Integrated Circuit for Offloading Physical Layer Logic for First Transmission Format to Separate Integrated Circuit
Clock Assignments for Programmable Logic Device
Application:
14/136,482 →
Publication:
US 2015/0178436
Group Based Routing in Programmable Logic Device
Messaging to Provide Data Link Integrity
Mechanism for Memory Reduction in Picture-in-Picture Video Generation
Computer Memory Test Structure
Hot-Socket Circuitry
Mechanism for Facilitating Dynamic Counter Synchronization and Packetization in High-Definition Multimedia Interface and Mobile High-Definition Link
Apparatus, System and Method for Providing Switching with a T-Coil Circuit
Apparatus, Method and System for Asymmetric, Full-Duplex Communication
Collector Current Driver for a Bipolar Junction Transistor Temperature Transducer
Low-Voltage Current Sense Amplifer
Power Delivery Over Digital Interaction Interface for Video and Audio (DiiVA)
Video Frame Synchronization
Application:
14/184,647 →
Publication:
US 2014/0168514
Test Solution for a Random Number Generator
Component Placement with Repacking for Programmable Logic Devices
Calibration of Single-Ended High-Speed Interfaces
Calibration of Single-Ended High-Speed Interfaces
Method and Apparatus for Implementing Wide Data Range and Wide Common-Mode Receivers
Communicating with MIPI-Compliant Devices Using Non-MIPI Interfaces
Communicating with MIPI-Compliant Devices Using Non-MIPI Interfaces
Patent:
9,009,379 →
Application:
14/223,096 →
Low-Cost Tracking System
High-Accuracy and Low-Power Tracking System for Mobile Devices
Calibrating a Retro-Directive Array for an Asymmetric Wireless Link
Transistor Matching for Generation of Precise Current Ratios
Communication of Multimedia Data Streams over Multiple Communication Lanes
Semiconductor Defect Characterization
Partition Based Design Implementation for Programmable Logic Devices
Transmission and Detection of Multi-Channel Signals in Reduced Channel Format
Error Detection and Mitigation in Video Channels
Application:
14/275,692 →
Publication:
US 2015/0326884
Encoding Guard Band Data For Transmission Via A Communications Interface Utilizing Transition-Minimized Differential Signaling (Tmds) Coding
Authentication Engine and Stream Cipher Engine Sharing in Digital Content Protection Architectures
Embedded Memory Testing Using Back-To-Back Write/Read Operations
Transmitting Apparatus with Source Termination
Configurable Multi-Dimensional Driver and Receiver
PVT Compensation Scheme for Output Buffers
Trigger Detection for Post Configuration Testing of Programmable Logic Devices
Application:
14/313,443 →
Publication:
US 2015/0370672
Holdtime Correction Using Input/Output Block Delay
Efficient Constant Multiplier Implementation for Programmable Logic Devices
Incrementer Absorption into Multiplier Logic for Programmable Logic Devices
Patent:
9,152,753 →
Application:
14/319,481 →
Sram with Two-Level Voltage Regulator
Mixed-Width Memory Techniques for Programmable Logic Devices
Cable with Circuitry for Communicating Performance Information
System-Level Dual-Boot Capability in Systems Having One or More Devices Without Native Dual-Boot Capability
Directional Beam Steering System and Method to Detect Location and Motion
Clock to Out Path Optimization
Application:
14/339,164 →
Publication:
US 2016/0026745
Bus-Based Clock to Out Path Optimization
Phase-Modulated On-Off Keying for Millimeter Wave Spectrum Control
Patent:
9,178,735 →
Application:
14/339,393 →
Collaborative Channel Sounding in Multi-Antenna Systems
Caching of Capabilities Information of Counterpart Device for Efficient Handshaking Operation
Charge Pump Calibration for Dual-Path Phase-Locked Loop
Linear Regulator with Improved Power Supply Ripple Rejection
Techniques for Fractional-N Phase Locked Loops
Frequency Response Compensation in a Digital to Analog Converter
Radio Frequency Interference Reduction In Multimedia Interfaces
System and Method for Transcoding Data
Frame Body Structure, Apparatus Frame Body, and Image Forming Apparatus
Compressed Video Transfer over a Multimedia Link
Application:
14/470,613 →
Publication:
US 2015/0256842
Compressed Blanking Period Transfer Over a Multimedia Link
Arbitration Signaling Within a Multimedia High Definition Link (Mhl 3) Device
Phase Relationship Control for Control Channel of a Multimedia Communication Link
Retry Disparity for Control Channel of a Multimedia Communication Link
Inter-Device Conflict Resolution on a Multimedia Link
Configurable Test Address And Data Generation For Multimode Memory Built-In Self-Testing
Application:
14/482,001 →
Publication:
US 2015/0310933
Enhanced Communication Link Using Synchronization Signal as Link Command
Application:
14/483,013 →
Publication:
US 2016/0072601
Electrical Connector with Optical Channel
Application:
14/502,928 →
Publication:
US 2016/0091669
Logic Absorption Techniques for Programmable Logic Devices
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Level Shifter With Low Static Power Dissipation
Application:
14/525,240 →
Publication:
US 2016/0118987
Meta-Stability Prevention for Oscillators
Application:
14/535,351 →
Publication:
US 2016/0134264
Class Ab Amplifier with Programmable Quiescent Current
Programmable Filter
Patent:
9,325,302 →
Application:
14/558,851 →
Determination of Physical Connectivity Status of Devices Based on Electrical Measurement
Electrical Duplex to Optical Conversion
Mechanism for Facilitating Dynamic Phase Detection with High Jitter Tolerance for Images of Media Streams
Sharing a Common Resource Via Multiple Interfaces
Application:
14/576,245 →
Publication:
US 2016/0179707
Reconfigurable and Scalable Hardware Management Architecture
System for Dynamic Audio Visual Capabilities Exchange
Control Target Selection
Displaying Multiple Videos on Sink Device Using Display Information of Source Device
Low Power Operations in a Wireless Tunneling Transceiver
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Registers for Post Configuration Testing of Programmable Logic Devices
Hotswap Operations for Programmable Logic Devices
Flexible Ripple Mode Device Implementation for Programmable Logic Devices
Multiple Mode Device Implementation for Programmable Logic Devices
High Speed Complementary Nmos Lut Logic
Shared Logic for Multiple Registers with Asynchronous Initialization
Pre-Processor and Post-Processor for Compression of 4:2:0 Encoded Video Streams with Video Compression Codecs Embedded within an Audio/Video Standard
Application:
61/943,267 →
Reversible Connector
Application:
61/947,704 →
Compressed Video Transfer Over Hdmi and Mhl
Application:
61/949,901 →
Error Correction for Transmission of Compressed Video Data over Standards-Defined Coded Audio/Video Links
Application:
61/973,837 →
(MHL) Connector Cable Detect, Cable Orientation Detect and/or Lane Re-Mapping
Application:
61/975,517 →
MHL3 Router without HDCP2.2 Decryption and Encryption Operation
Application:
61/979,477 →
TDD over 5-Pin Interface
Application:
61/979,483 →
Lip Sync Delay Compensation
Application:
61/988,812 →
System for Dynamic Capabilities, Status, and Metadata Exchange
Application:
61/989,409 →
Topology Discovery
Application:
61/989,411 →
Streaming Data and Metadata Synchronization
Application:
61/989,415 →
Control Target Selection
Application:
61/989,417 →
Stream Creation with Limited Topology Information
Application:
61/991,126 →
Secure Control Communication Between an Application Processor and a Transmitter
Application:
62/061,630 →
Metadata Transfer for HDMI/MHL
Application:
62/075,554 →
High-bandwidth Digital Content Protection over Audio Return Channel
Application:
62/089,767 →
I/Q Imbalance Correction for the Combination of Multiple Radio Frequency Frontends
Application:
62/100,841 →
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 6, 2014
From: TRUONG, KEITH; SHARPE-GEISLER, BRAD; LALL, RAVI; TRAN, GIAP
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 031894/0369 →
Security Interest
Mar 17, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035220/0048 →
Security Interest
Mar 24, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035309/0142 →
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →