Sense amplifier systems and methods
View Patent ↗Systems and methods including sense amplifiers for various applications. For example, in accordance with an embodiment of the present invention, a sense amplifier for a memory array having an associated precharge circuit and a read completion detection circuit.
1. A memory array comprising:
a plurality of bitlines;
a plurality of sense amplifiers coupled to the bitlines and adapted to read data provided on the bitlines;
a plurality of precharge circuits adapted to precharge the bitlines; and
a plurality of inverters coupled to the bitlines and adapted to provide output signals based on signal levels on the bitlines.
2. The memory array of claim 1 including:
a plurality of logic gates adapted to receive the output signals from the inverters and to provide trip signals based on the output signals; and
a plurality of latches adapted to store the output signals from at least one of the inverters under control of the trip signals.
3. The memory array of claim 2 , wherein the sense amplifiers are disabled about when corresponding trip signals transition to a new value.
4. The memory array of claim 2 , wherein the precharge circuits are enabled to precharge the bitlines about when corresponding trip signals transition to a new value.
5. The memory array of claim 2 , further comprising a plurality of sense amplifier controllers each associated with one or more of the sense amplifiers, wherein a sense amplifier controller controls the enabling and disabling of an associated sense amplifier and precharge circuit based on an associated trip signal.
6. The memory array of claim 5 , further comprising a plurality of column multiplexers adapted to couple selected data lines to the bitlines of sense amplifiers, wherein the column multiplexers are enabled by sense amplifier controllers.
7. A memory array comprising:
a plurality of bitlines;
a plurality of sense amplifiers coupled to the bitlines and adapted to read data provided on the bitlines;
a plurality of precharge circuits adapted to precharge the bitlines;
a plurality of inverters coupled to the bitlines and adapted to provide output signals based on signal levels on the bitlines;
a plurality of logic gates adapted to receive the output signals from the inverters and to provide trip signals based on the output signals; and
a plurality of latches adapted to store the output signals from at least one of the inverters under control of corresponding trip signals,
wherein the trip signals transition to a first value about when the bitlines are precharged and transition to a second value about when the sense amplifiers read the data on the bitlines.
8. The memory array of claim 7 , wherein the sense amplifiers are disabled about when corresponding trip signals transition to the second value.
9. The memory array of claim 7 , wherein the precharge circuits are enabled to precharge the bitlines about when corresponding trip signals transition to the second value.
10. A memory array comprising:
a plurality of bitlines;
a plurality of sense amplifiers coupled to the bitlines and adapted to read data provided on the bitlines;
a plurality of precharge circuits adapted to precharge the bitlines;
a plurality of inverters coupled to the bitlines and adapted to provide output signals based on signal levels on the bitlines;
a plurality of logic gates adapted to receive the output signals from the inverters and to provide trip signals based on the output signals; and
a plurality of sense amplifier controllers each associated with one or more of the sense amplifiers, wherein a sense amplifier controller controls the enabling and disabling of an associated sense amplifier and precharge circuit based on an associated trip signal.