Patent Assignment
Reel/Frame 035223/0001
Security Interest
Recorded: 2015-03-18
Pages: 83
Assignors
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2015-03-10
SIBEAM, INC.
Executed: 2015-03-10
SILICON IMAGE, INC.
Executed: 2015-03-10
DVDO, INC.
Executed: 2015-03-10
Assignee
JEFFERIES FINANCE LLC
520 MADISON AVENUE, NEW YORK, NEW YORK, 10022
Covered Properties
(104)
Data Decompression
Patent:
7,382,293 →
Application:
11/054,750 →
Data Decompression
Patent:
7,589,648 →
Application:
11/054,855 →
Distributed Multiple-Channel Alignment Scheme
Output Impedance Measurement Techniques
Patent:
7,057,397 →
Application:
11/070,926 →
Differential Input Receiver with Programmable Failsafe
Patent:
7,245,154 →
Application:
11/071,356 →
Detection of Unknown Symbol Rate in a Digitally Modulated Signal
Patent:
7,376,204 →
Application:
11/083,625 →
In-System Programming of Non-Jtag Device Using Spi and Jtag Interfaces of Fpga Device
Patent:
7,265,578 →
Application:
11/098,713 →
In-System Programming of a Non-Compliant Device Using Multiple Interfaces of a Pld
Patent:
7,397,274 →
Application:
11/100,718 →
Fast Processing Path Using Field Programmable Gate Array Logic Unit
Analog-To-Digital Systems and Methods
Patent:
7,630,464 →
Application:
11/109,301 →
Field Programmable Gate Array
Electronic Switch Having Extended Voltage Range
Patent:
7,400,171 →
Application:
11/121,326 →
Programmable I/O Interfaces for Fpgas and Other Plds
Patent:
7,009,423 →
Application:
11/134,152 →
Design Features for Testing Integrated Circuits
Patent:
7,685,483 →
Application:
11/157,345 →
Decoding Systems and Methods
Patent:
7,378,879 →
Application:
11/157,349 →
Programmable Interconnect Architecture for Programmable Logic Devices
Patent:
7,256,613 →
Application:
11/165,709 →
Programmable Logic Device with a Double Data Rate Sdram Interface
Patent:
7,342,838 →
Application:
11/165,853 →
Signal Monitoring Systems and Methods
Patent:
7,519,139 →
Application:
11/185,242 →
Output Clock Phase-Alignment Circuit
Patent:
7,253,674 →
Application:
11/187,114 →
Address Decoding Systems and Methods
Receiver for Differential and Reference-Voltage Signaling with Programmable Common Mode
Patent:
7,505,752 →
Application:
11/189,067 →
Programmable Termination for Single-Ended and Differential Schemes
Patent:
7,262,630 →
Application:
11/194,356 →
Bitline Twisting Scheme for Multiport Memory
Patent:
7,414,913 →
Application:
11/194,871 →
Clock-And-Data-Recovery System Having a Multi-Phase Clock Generator for One or More Channel Circuits
Input/Output Systems and Methods
Patent:
7,411,419 →
Application:
11/200,941 →
Programmable Logic Device with Enhanced Logic Block Architecture
Patent:
7,295,035 →
Application:
11/200,983 →
Flash Memory Erase Verification Systems and Methods
Patent:
7,187,586 →
Application:
11/201,620 →
Correlator Having User-Defined Processing
Zero-Power Programmable Memory Cell
Patent:
40,311 →
Application:
11/206,282 →
Circuit Layout for Improved Performance While Preserving or Improving Density
Patent:
7,301,182 →
Application:
11/226,695 →
Data Transfer Verification Systems and Methods
Patent:
7,167,405 →
Application:
11/230,087 →
Programmable Logic Device with Power-Saving Architecture
Patent:
7,376,037 →
Application:
11/235,616 →
Electrostatic Protection Systems and Methods
Configuring Fpgas and the Like Using One or More Serial Memory Devices
Patent:
7,088,132 →
Application:
11/243,255 →
Address Isolation for User-Defined Configuration Memory in Programmable Devices
Patent:
7,196,963 →
Application:
11/251,682 →
Clock Reset Address Decoder for Block Memory
Field Programmable Gate Array
Fast-Carry Arithmetic Circuit Using a Multi-Input Look-Up Table
Patent:
7,685,215 →
Application:
11/257,137 →
Pulse-Generation Circuit with Multi-Delay Block and Set-Reset Latches
Patent:
7,317,343 →
Application:
11/257,641 →
Control Signal Generation for a Low Jitter Switched-Capacitor Frequency Synthesizer
Patent:
7,212,051 →
Application:
11/260,097 →
Digital I/O Timing Control
Interface Block Architectures
Patent:
7,327,159 →
Application:
11/287,720 →
Pseudo-Dynamic Word-Line Driver
Transparent Field Reconfiguration for Programmable Logic Devices
Patent:
7,538,574 →
Application:
11/293,941 →
Temperature-Independent, Linear on-Chip Termination Resistance
Jitter Tolerant Delay-Locked Loop Circuit
Systems and Methods for Reducing Static Phase Error
Phase-Locked Loop Systems and Methods
Dynamic Over-Voltage Protection Scheme for Interface Circuitry
Patent:
7,547,995 →
Application:
11/345,713 →
Efficient Configuration of Daisy-Chained Programmable Logic Devices
Reconfiguration of Programmable Logic Devices
Patent:
7,375,549 →
Application:
11/350,436 →
Memory Cell Comprising an Otp Nonvolatile Memory Unit and a Sram Unit
Programmable Logic Devices with Distributed Memory and Non-Volatile Memory
Patent:
7,355,441 →
Application:
11/360,337 →
Auto Recovery from Volatile Soft Error Upsets (Seus)
Patent:
7,596,744 →
Application:
11/361,584 →
Comparator Systems and Methods
Patent:
7,446,573 →
Application:
11/361,643 →
Dynamic Phase Offset Measurement
Programmable Logic Devices with User Non-Volatile Memory
Patent:
7,554,358 →
Application:
11/397,985 →
Programmable Logic Devices with Transparent Field Reconfiguration
Patent:
7,459,931 →
Application:
11/398,437 →
Selective Programming of Non-Volatile Memory Facilitated by Security Fuses
Patent:
7,623,378 →
Application:
11/416,881 →
Key Generation for Advanced Encryption Standard (Aes) Decryption and the Like
Clock Distribution Chip for Generating Both Zero-Delay and Non-Zero-Delay Clock Signals
Patent:
7,657,773 →
Application:
11/425,881 →
Sense Amplifier Systems and Methods
Selective Loading of Configuration Data into Configuration Memory Cells
Patent:
7,411,417 →
Application:
11/442,186 →
Programmable Logic Device Architecture with Multiple Slice Types
Patent:
7,378,872 →
Application:
11/445,620 →
Programmable Logic Devices with Custom Identification Systems and Methods
Patent:
7,546,498 →
Application:
11/446,308 →
Flexible Memory Architectures for Programmable Logic Devices
Patent:
7,495,970 →
Application:
11/446,309 →
Logic Block Control Architectures for Programmable Logic Devices
Patent:
7,397,276 →
Application:
11/446,351 →
Dual Slice Architectures for Programmable Logic Devices
Patent:
7,385,417 →
Application:
11/446,542 →
Programmable Logic Device Providing a Serial Peripheral Interface
Patent:
7,378,873 →
Application:
11/446,548 →
Programmable Logic Device Methods and System for Providing Multi-Boot Configuration Data Support
Patent:
7,631,223 →
Application:
11/447,591 →
Programmable Logic Device and Method of Testing
Patent:
7,463,060 →
Application:
11/452,714 →
Upgradeable and Reconfigurable Programmable Logic Device
Integrated Circuits and Complementary Cmos Circuits for Frequency Dividers
Patent:
7,411,432 →
Application:
11/461,222 →
Method and Systems to Align Output Signals of an Analog-to-Digital Converter
Patent:
7,348,914 →
Application:
11/477,759 →
Flash Memory Array with Independently Erasable Sectors
Patent:
7,636,259 →
Application:
11/487,647 →
Negative Voltage Blocking for Embedded Memories
Patent:
7,512,015 →
Application:
11/487,751 →
Charge Pump with Four-Well Transistors
Switch Sequencing Circuit Systems and Methods
Methods and Systems for Storing a Security Key Using Programmable Fuses
Patent:
7,675,313 →
Application:
11/498,645 →
Area Efficient Routing Architectures for Programmable Logic Devices
Patent:
7,605,606 →
Application:
11/498,646 →
Clock Systems and Methods
Patent:
7,456,672 →
Application:
11/530,620 →
Efficient Bitstream Compression
Patent:
7,511,641 →
Application:
11/533,188 →
Multiple Communication Channel Configuration Systems and Methods
Patent:
7,831,754 →
Application:
11/551,459 →
Multiplexer Initialization Systems and Methods
Patent:
7,663,401 →
Application:
11/556,528 →
Programmable Logic Device Programming Verification Systems and Methods
Patent:
7,725,803 →
Application:
11/557,808 →
Programmable Current Output and Common-Mode Voltage Buffer
Patent:
7,535,258 →
Application:
11/593,274 →
Data Transfer Verification Systems and Methods
Patent:
7,623,391 →
Application:
11/624,021 →
Low Static Current Drain Logic Circuit
Output Buffer with Digital Slew Control
Patent:
7,443,192 →
Application:
11/643,288 →
High Fan-Out Signal Routing Systems and Methods
Patent:
7,576,563 →
Application:
11/671,948 →
Flash Memory Erase Verification Systems and Methods
Patent:
7,313,025 →
Application:
11/675,246 →
Diagonal Interleaved Parity Calculator
Patent:
7,430,706 →
Application:
11/676,071 →
Redundant Configuration Memory Systems and Methods
Logic Analyzer Systems and Methods for Programmable Logic Devices
Patent:
7,536,615 →
Application:
11/691,003 →
Logic Analyzer Systems and Methods for Programmable Logic Devices
Patent:
7,743,296 →
Application:
11/691,040 →
Clock Boosting Systems and Methods
Patent:
7,509,598 →
Application:
11/737,702 →
Integrated Circuit Temperature Sensor Systems and Methods
Patent:
7,632,011 →
Application:
11/750,616 →
Self-Verification of Configuration Memory in Programmable Logic Devices
Patent:
7,401,280 →
Application:
11/750,790 →
Soft Error Detection Logic Testing Systems and Methods
Patent:
8,065,574 →
Application:
11/760,411 →
Programmable Logic Device Providing Serial Peripheral Interfaces
Patent:
7,570,078 →
Application:
11/761,221 →
Distributed Front-End Fifo for Source-Synchronized Interfaces with Non-Continuous Clocks
Patent:
7,573,770 →
Application:
11/778,457 →
Compression and Decompression of Configuration Data for Programmable Logic Devices
Patent:
7,446,679 →
Application:
11/779,246 →
Weight Based Look Up Table Collapsing for Programmable Logic Devices
Patent:
7,681,160 →
Application:
11/863,016 →
Variable Data Width Memory Systems and Methods
Patent:
7,539,076 →
Application:
11/865,556 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Mar 6, 2015
From: LATTICE SEMICONDUCTOR LIMITED
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 035101/0559 →
Assignment of Assignor's Interest
May 4, 2018
From: KILOPASS TECHNOLOGY, INC.
To: SYNOPSYS, INC.
Reel/Frame 046099/0269 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Change of Name
May 13, 2024
From: GENESYS TELECOMMUNICATIONS LABORATORIES, INC.
To: GENESYS CLOUD SERVICES, INC.
Reel/Frame 067391/0077 →