Negative voltage blocking for embedded memories
View Patent ↗In one embodiment, a memory is provided that includes: a memory cell array adapted to be programmed with a positive voltage from a positive-negative node and to be erased with a negative voltage from the positive-negative node; a negative voltage blocking circuit; and a positive voltage source operable coupled to the negative voltage blocking circuit, the positive voltage source operable to provide the positive voltage to the positive-negative node through the negative voltage blocking circuit, wherein the negative voltage blocking circuit is adapted to prevent the negative voltage from coupling from the positive-negative node to the positive voltage source.
1. A memory, comprising:
a memory cell array adapted to be programmed with a positive voltage from a positive-negative node and to be erased with a negative voltage from the positive-negative node;
a negative voltage blocking circuit; and
a positive voltage source coupled to the negative voltage blocking circuit, the positive voltage source operable to provide the positive voltage to the positive-negative node through the negative voltage blocking circuit, wherein the negative voltage blocking circuit is adapted to prevent the negative voltage from coupling from the positive-negative node to the positive voltage source.
2. The memory of claim 1 , wherein the memory cell array is a FLASH memory cell array.
3. The memory of claim 1 , wherein the positive voltage source is a positive voltage charge pump.
4. The memory of claim 1 , further comprising a negative voltage charge pump operable to provide the negative voltage to the positive-negative node.
5. The memory of claim 1 , wherein the negative voltage blocking circuit comprises a transmission gate coupled between the positive voltage source and the positive-negative voltage node.
6. The memory of claim 5 , wherein the memory cell array and an NMOS transistor in the transmission gate are all located within a triple p-well.
7. The memory of claim 6 , wherein the positive voltage source and a PMOS transistor in the transmission gate are all located outside the triple p-well.
8. The memory of claim 6 , wherein the positive-negative node and an inner p-well of the triple p-well are coupled during an erase operation in which the positive-negative node is driven with the negative voltage.
9. The memory of claim 7 , further comprising a positive voltage switch operable to drive a gate of the PMOS transistor during a programming operation in which the positive-negative node is driven with the positive voltage.
10. The memory of claim 1 , wherein the positive voltage is approximately positive 10 volts and the negative voltage is approximately negative 10 volts.
11. A method of operating an array of memory cells, comprising:
driving a first set of cells within the array with a negative voltage, wherein the negative voltage couples from a negative voltage source through a positive-negative node to the first set of cells;
driving a second set of cells within the array with a positive voltage, wherein the positive voltage couples from a positive voltage source through the positive-negative node to the second set of cells; and
blocking the negative voltage from coupling to the positive voltage source while the first set of cells are driving with the negative voltage.
12. The method of claim 11 , wherein the memory is a FLASH memory and the first set of cells are driven with the negative voltage so as to erase the first set of cells.
13. The method of claim 12 , wherein the second set of cells are driven with the positive voltage so as to program the second set of cells.
14. The method of claim 11 , wherein blocking the negative voltage comprises shutting off a transmission gate.
15. The method of claim 14 , wherein shutting off the transmission gate comprises coupling the negative voltage to a gate of an NMOS transistor in the transmission gate.
16. The method of claim 15 , wherein shutting off the transmission gate further comprises coupling the negative voltage to a p-well holding the NMOS transistor.
17. A programmable logic device, comprising:
a logic core;
a non-volatile memory for holding configuration data for the logic core;
a positive voltage source operable to program the non-volatile memory with a positive voltage;
a negative voltage source operable to erase the non-volatile memory with a negative voltage; and
a blocking circuit operable to couple the positive voltage from the positive voltage source to the non-volatile memory and to isolate the positive voltage source from the negative voltage while the negative voltage source is operable to erase the non-volatile memory the negative voltage.
18. The programmable logic device of claim 17 , wherein the non-volatile memory is a FLASH memory.
19. The programmable logic device of claim 17 , wherein the blocking circuit comprises a transmission gate.