Programmable logic device methods and system for providing multi-boot configuration data support
View Patent ↗Various techniques are disclosed herein to provide an improved approach to the loading of configuration data into configuration memory of programmable logic devices. For example, in accordance with one embodiment of the present invention a method of configuring a programmable logic device includes reading a first bitstream from a first memory block of an external memory device. The first bitstream is checked for errors and a second bitstream is read from a second memory block of the external memory device if an error is detected. Configuration memory of the programmable logic device is programmed with configuration data provided in one of the first bitstream and the second bitstream.
1. A programmable logic device comprising:
a bus interface adapted to interface with an external memory device;
configuration memory adapted to store configuration data to configure the programmable logic device for its intended function; and
a bus interface controller adapted to:
read via the bus interface a first bitstream from a first memory block of the external memory device,
check the first bitstream for errors,
if an error is detected in the first bitstream:
read via the bus interface a second bitstream from a second memory block of the external memory device,
check the second bitstream for errors,
if no error is detected in the second bitstream:
initiate programming of the configuration memory with configuration data provided in the second bitstream, and
if an error is detected in the second bitstream:
stop attempting to program the configuration memory with configuration data from the external memory device.
2. The programmable logic device of claim 1 , wherein the first bitstream comprises primary boot data and the second bitstream comprises default boot data.
3. The programmable logic device of claim 1 , further comprising user-defined logic adapted to provide the bus interface controller with an address of the first memory block, wherein the first bitstream comprises alternate configuration data and the second bitstream comprises default boot data.
4. The programmable logic device of claim 1 , wherein the bus interface controller is further adapted to read a third bitstream from a third memory block of the external memory device, wherein an address of one of the first and second memory blocks is provided by a jump command provided in the third bitstream.
5. The programmable logic device of claim 1 , wherein the bus interface controller is further adapted to provide a select signal to the external memory device, wherein the external memory device is one of a plurality of external memory devices adapted to receive select signals from the programmable logic device.
6. The programmable logic device of claim 1 , wherein the bus interface is a serial interface and the external memory is a non-volatile memory.
7. The programmable logic device of claim 1 , wherein the bus interface is a parallel interface and the external memory is a non-volatile memory.
8. The programmable logic device of claim 1 , wherein the bus interface controller is further adapted to read the first bitstream in response to one of a powering up of the programmable logic device and an instruction received by the programmable logic device.
9. The programmable logic device of claim 1 , wherein if an error is detected in the first bitstream, the bus interface controller is further adapted to perform the read of the second bitstream and to initiate the programming of the configuration memory without permitting the programmable logic device to operate in accordance with any configuration data stored in the configuration memory.
10. A programmable logic device comprising:
a bus interface adapted to interface with non-volatile memory;
configuration memory adapted to store configuration data to configure the programmable logic device for its intended function; and
a bus interface controller adapted to:
read via the bus interface a first bitstream from a first memory block of the non-volatile memory,
check the first bitstream for errors,
if an error is detected in the first bitstream:
read via the bus interface a second bitstream from a second memory block of the non-volatile memory,
check the second bitstream for errors,
if no error is detected in the second bitstream:
initiate programming of the configuration memory with configuration data provided in the second bitstream, and
if an error is detected in the second bitstream:
stop attempting to program the configuration memory with configuration data from the non-volatile memory.
11. The programmable logic device of claim 10 , wherein the bus interface is adapted to interface with non-volatile memory external to the programmable logic device.