Logic analyzer systems and methods for programmable logic devices

1. A computer-readable medium on which is stored a computer program that, when executed by a computer, performs logic analysis within a programmable logic device (PLD), the method comprising:

receiving trigger unit information of a logic analyzer via a graphical user interface for monitoring internal programmable logic device (PLD) signals and providing trigger unit output signals for the corresponding trigger units;

receiving trigger expression information of the logic analyzer via the graphical user interface as a text string of logic operators and operands representing a trigger expression, wherein the operands represent the trigger unit output signals; and

programming a memory within the PLD with a truth table based on the text string, with the trigger unit output signals to be provided to the programmed memory as address signals.

2. The computer-readable medium of claim 1 , wherein the text string comprises a series of logic sub-expressions having count operators, and wherein the method further comprises receiving event counter information via the graphical user interface based on the count operators.

3. The computer-readable medium of claim 1 , wherein the method further comprises:

receiving event counter information via the graphical user interface for the trigger expression information;

receiving samples per trigger information via the graphical user interface for the trigger expression information; and

receiving trigger position information via the graphical user interface for the trigger expression information.

4. The computer-readable medium of claim 1 , wherein the trigger unit information comprises logical operators to apply to the internal PLD signals.

5. The computer-readable medium of claim 1 , wherein the trigger expression information comprises a series of logic sub-expressions entered by a user within a text string box.

6. The computer-readable medium of claim 1 , wherein one of the internal PLD signals includes a serial bit pattern, and wherein the method further comprises programming the PLD to perform a compare operation of a given bit pattern to the serial bit pattern to determine a match condition.

7. A system comprising:

a programmable logic device (PLD);

means for entering trigger unit information directed to internal PLD signals to provide trigger unit output signals based on the internal PLD signals for the corresponding trigger units;

means for entering trigger expression information as a text string of logic operators and operands, wherein the operands represent the trigger unit output signals;

means for generating configuration data based on the trigger unit information and the trigger expression information, wherein the configuration data for a trigger expression of the trigger expression information configures a memory of the PLD;

means for providing the configuration data to the PLD, wherein the trigger expression is stored within the memory of the PLD; and

means for routing the trigger unit output signals to the memory as address signals for the trigger expression.

8. The system of claim 7 , wherein the generating means further comprises means for executing the text string with a programming language to create truth tables based on the text string.

9. The system of claim 7 , wherein the text string comprises a series of logic sub-expressions having count operators, and wherein the trigger expression information further comprises event counter information based on the count operators, samples per trigger information, and trigger position information.

10. The system of claim 7 , wherein one of the internal PLD signals includes a serial bit pattern, and wherein the configuration data is adapted to program the PLD to perform a compare operation of a given bit pattern to the serial bit pattern to determine a match condition.

11. A programmable logic device comprising:

a plurality of trigger unit circuits of a logic analyzer, the trigger unit circuits adapted to provide trigger unit output signals based on internal PLD signals;

memory; and

a trigger expression circuit responsive to a text string of logic operators and operands representing a trigger expression of the logic analyzer, wherein the operands represent trigger unit output signals, the trigger expression circuit adapted to program the memory with a truth table based on the text string, with the trigger unit output signals to be provided to the programmed memory as address signals.

12. The programmable logic device of claim 11 , wherein the memory is programmed with a truth table based on the text string.

13. The programmable logic device of claim 12 , wherein the truth table is implemented as a lookup table in the memory.