Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits

1. A clock-and-data recovery (CDR) system, comprising:

a clock generator adapted to generate a plurality of phase-offset clock signals; and

one or more channel circuits, each channel circuit adapted to generate an output data stream and a recovered clock signal based on an input data signal, wherein each channel circuit comprises:

a data register for each phase-offset clock signal, the data register adapted to generate an output signal based on the level of the corresponding phase-offset clock signal at a transition in the input data signal;

a logic circuit adapted to process the output signals from the data registers to select one of the phase-offset clock signals as a sampling clock signal; and

a data sampler adapted to sample the input data signal based on the sampling clock signal to generate the output data stream and generate the recovered clock signal based on the sampling clock signal, wherein:

each channel circuit comprises first and second banks of data registers;

the CDR system is adapted to be selectively configured to operate in one of a first mode and a second mode;

in the first mode, the CDR system is selectively configured such that:

the clock generator generates a first set of phase-offset clock signals;

the first set of phase-offset clock signals is applied to both the first and second banks of data registers; and

the logic circuit selects a data register output signal corresponding to a phase-offset clock signal of the first set of phase-offset clock signals as the sampling clock signal; and

in the second mode, the CDR system is selectively configured such that:

the clock generator generates the first set of phase-offset clock signals and a second set of phase-offset clock signals;

the first set of phase-offset clock signals is applied to the first bank of data registers;

the second set of phase-offset clock signals is applied to the second bank of data registers; and

the logic circuit selects a data register output signal corresponding to a phase-offset clock signal of the first and second sets of phase-offset clock signals as the sampling clock signal.

2. The clock-and-data recovery system of claim 1 , further comprising a clock divider adapted to divide the sampling clock signal by a specified divisor value to generate the recovered clock signal.

3. The clock-and-data recovery system of claim 2 , wherein the data sampler is adapted to generate the output data stream as a parallelized data stream.

4. The clock-and-data recovery system of claim 1 , wherein:

each data register is an edge-triggered flip-flop, having a data input port, a clock input port, and a data output port;

each flip-flop is connected to receive the corresponding phase-offset clock signal at its data input port and the input data signal at its clock input port; and

each flip-flop is adapted to present values of the phase-offset clock signal at its data output port at certain transitions in the input data signal.

5. The clock-and-data recovery system of claim 4 , wherein the flip-flops are triggered by rising edges in the input data signal.

6. The clock-and-data recovery system of claim 1 , wherein the clock generator is a delay-locked loop (DLL).

7. The clock-and-data recovery system of claim 6 , wherein:

the DLL comprises a phase detector and a delay chain;

the plurality of phase-offset clock signals are output from different selected delay elements along the delay chain; and

the phase detector is adapted to control the selection of the different delay elements based on a phase difference between a received reference clock and one of the phase-offset clock signals.

8. The clock-and-data recovery system of claim 7 , wherein the number of delay elements in the delay chain and the number of phase-offset clock signals output from the delay chain are metal mask programmable.

9. The invention of claim 1 , wherein the CDR system further comprises a multiplexer for each data register in the second bank of data registers, wherein:

the multiplexer is connected to receive a phase-offset clock signal of the first set and a corresponding phase-offset clock signal of a second set; and

the multiplexer is adapted to provide one of the received phase-offset clock signals to the corresponding data register in the second bank of data registers depending on whether the CDR system is configured to operate in the first mode or the second mode.

10. The clock-and-data recovery system of claim 1 , comprising two or more of the channel circuits.

11. The clock-and-data recovery system of claim 10 , wherein the input data signals associated with at least two of the channel circuits have different data rates.