Differential input receiver with programmable failsafe

1. A circuit, comprising:

a differential input receiver having a first input terminal and a second input terminal;

a first programmable switch coupled to the first input terminal and coupled through a first resistor to a first voltage such that if the first programmable switch is closed, the first input terminal is pulled towards the first voltage;

a second programmable switch coupled to the second input terminal and coupled through a second resistor to a second voltage such that if the second programmable switch is closed, the second input terminal is pulled towards the second voltage;

a third programmable switch coupled to the first input terminal and coupled through a third resistor to the second voltage such that if the third programmable switch is closed, the first input terminal is pulled to the second voltage; and

a fourth programmable switch coupled to the second input terminal and coupled through a fourth resistor to the first voltage such that if the fourth switch is closed, the second input terminal is pulled towards the first voltage;

wherein the first and second programmable switches are programmed to be closed and the third and fourth programmable switches are programmed to be open during a first differential input mode of operation in which the differential input receiver processes differential input signals provided to the first and second input terminals.

2. The circuit of claim 1 , wherein the first and second programmable switches are programmed to be open and the third and fourth programmable switches are programmed to be closed during a second differential input mode of operation in which the differential input receiver processes differential input signals provided to the first and second input terminals.

3. The circuit of claim 1 , further comprising:

a first memory cell operable to store a first control signal for controlling the first programmable switch; the first memory cell being configured to provide the programming of the first programmable switch.

4. The circuit of claim 3 , further comprising:

a second memory cell operable to store a second control signal for controlling the second programmable switch; the second memory cell being configured to provide the programming of the second programmable switch.

5. The circuit of claim 4 , wherein the circuit is included within a programmable logic device and wherein the first and second memory cells are within a configuration memory for the programmable logic device.

6. The programmable logic device of claim 5 , wherein the configuration memory is an internal memory of the programmable logic device.

7. The circuit of claim 1 , wherein the first resistor is a weak pull-up resistor and wherein the second resistor is a weak pull-down resistor.

8. The circuit of claim 1 , wherein a termination resistor couples across the first and second input terminals.

9. A method of biasing a differential input receiver having a first input terminal and a second input terminal, comprising:

closing a first switch from a first set of two switches coupled to the first input terminal to couple the first input terminal to a first signal source, a remaining switch in the first set of switches being coupled to the second signal source;

closing a second switch from a second set of two switches coupled to the second input terminal to couple the second input terminal to a second signal source, a remaining switch in the second set of switches being coupled to the first signal source; and

while the first and second switches are closed, operating the differential input receiver in the absence of differential input signals driving the first and second input terminals,

wherein the differential input receiver is biased into a known logical state determined by the first and second signal sources.

10. The method of claim 9 , wherein the first and second signals sources are voltages.

11. The method of claim 10 , wherein the first signal source is a supply voltage and the second signal source is ground.

12. The method of claim 9 , wherein closing the first switch and closing the second switch includes programming memory cells that control the operation of the switches.

13. The method of claim 12 , wherein the differential input receiver is integrated within a programmable logic device (PLD), the method including providing to the PLD a configuration bitstream that includes bits to program the memory cells.

14. The method of claim 9 , wherein the differential input receiver is integrated within a programmable logic device having a logic core, the method further comprising:

configuring the logic core to enable the closing of the first and second switches.

15. A programmable circuit including a differential input receiver having a first input terminal and a second input terminal, comprising:

a first means having a first state for programmably driving a potential of the first input terminal of the receiver towards a power supply voltage and having a second state for programmably driving a potential of the first input terminal towards ground; and

a second means having a first state for programmably driving a potential of the second input terminal of the receiver towards ground and having a second state for programmably driving a potential of the second input terminal towards the power supply voltage,

wherein, while the programmable circuit is in a first differential input mode of operation, the first and second means are in the first state.

16. The programmable circuit of claim 15 , wherein, while the programmable circuit is in a second differential input mode of operation, the first and second means are in the second state.

17. The programmable circuit of claim 15 , wherein the programmable circuit is a programmable logic device.

18. The programmable logic device of claim 17 , wherein a configuration memory for the programmable logic device is configured to provide control signals for controlling whether the first and second means are in the first state.

19. The programmable circuit of claim 15 , wherein the differential input receiver is one of a low voltage differential signaling (LVDS) receiver and a low voltage positive emitter coupled logic (LVPECL) receiver.