Upgradeable and reconfigurable programmable logic device
View Patent ↗Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.
1. A programmable logic device comprising:
a first data port;
volatile memory adapted to configure the programmable logic device based on configuration data stored by the volatile memory;
non-volatile memory adapted to store configuration data; and
a command decoder operable to control transfer of configuration data from the non-volatile memory to the volatile memory and from the volatile memory to the non-volatile memory and further operable to control transfer of configuration data from the first data port to the volatile memory and from the first data port to the non-volatile memory.
2. The programmable logic device of claim 1 including a second data port, the command decoder further operable to control transfer of configuration data from the first data port or the second data port to the volatile memory and from the first data port or the second data port to the non-volatile memory.
3. The programmable logic device of claim 2 , wherein the first data port is a JTAG port and the second data port is a CPU port.
4. The programmable logic device of claim 1 , further comprising core logic adapted to be configured by the configuration data stored in the volatile memory.
5. The programmable logic device of claim 1 , wherein the volatile memory comprises static random access memory and the non-volatile memory comprises flash memory.
6. The programmable logic device of claim 1 , wherein the non-volatile memory is further adapted to store security bits that can be set to prevent unauthorized reading of the configuration data from the programmable logic device.
7. The programmable logic device of claim 1 , wherein the programmable logic device is an FPGA.
8. A programmable logic device comprising:
a data port;
volatile memory adapted to configure the programmable logic device based on configuration data stored by the volatile memory;
non-volatile memory adapted to store configuration data; and
means for controlling transfer of configuration data from the non-volatile memory to the volatile memory and from the volatile memory to the non-volatile memory and for controlling transfer of configuration data from the data port to the volatile memory and from the data port to the non-volatile memory.
9. The programmable logic device of claim 8 , further comprising core logic adapted to be configured by the configuration data stored in the volatile memory.
10. The programmable logic device of claim 8 , wherein the volatile memory comprises static random access memory and the non-volatile memory comprises flash memory.
11. The programmable logic device of claim 8 , wherein the non-volatile memory is further adapted to store security bits that can be set to prevent unauthorized reading of the configuration data from the programmable logic device.
12. The programmable logic device of claim 8 , wherein the programmable logic device is an FPGA.
13. A programmable logic device comprising:
volatile memory adapted to configure the programmable logic device based on configuration data stored by the volatile memory;
non-volatile memory adapted to store configuration data;
a data register coupled between the volatile memory and non-volatile memory; and
a command decoder operable to control transfer of configuration data via the data register from the non-volatile memory to the volatile memory and from the volatile memory to the non-volatile memory.
14. The programmable logic device of claim 13 including a first data port, the command decoder further operable to control transfer of configuration data from the first data port to the volatile memory and from the first data port to the non-volatile memory.
15. The programmable logic device of claim 14 including a second data port, the command decoder further operable to control transfer of configuration data from the first data port or the second data port to the volatile memory and from the first data port or the second data port to the non-volatile memory.
16. The programmable logic device of claim 15 , wherein the first data port is a JTAG port and the second data port is a CPU port.
17. The programmable logic device of claim 13 , wherein the volatile memory comprises static random access memory and the non-volatile memory comprises flash memory.