Pseudo-dynamic word-line driver
View Patent ↗In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of a larger device, such as an FPGA. The word-line driver has a feed-back latch for each word-line that ensures that the word-line is not energized when that word-line is not selected for access. By controlling the feed-back latch using a decoded address bit value rather than a pre-charged enable signal as do some prior-art dynamic word-line drivers, the word-line driver prevents undesirable energizing of multiple word-lines. The word-line driver can be implemented using less layout area and less power than some analogous prior-art static word-line drivers.
1. An integrated circuit having a word-line driver adapted to receive a set of decoded bits (e.g., D 0 , D 1 , D 74 , D 118 ) and control a set of word-lines (e.g., WL 0 , WL 1 ), the word-line driver comprising:
a first set of circuitry (e.g., 602 – 608 ) adapted to receive and process a first subset of one or more decoded bits (e.g., D 74 , D 118 ) and connected to a first node (e.g., W) in the word-line driver; and
a second set of circuitry (e.g., 614 – 628 ) connected to the first node and adapted to receive and process a second subset of decoded bits (e.g., D 0 , D 1 ) to control the set of word-lines, wherein, for each word-line (e.g., WL 0 ), the second set of circuitry comprises a corresponding feed-back latch (e.g., 622 , 626 , 628 ) controlled by a corresponding decoded bit (e.g., D 0 ) and adapted to drive the corresponding word-line low if the corresponding decoded bit indicates that the corresponding word-line is not selected.
2. The invention of claim 1 , wherein the first set of circuitry is shared by all of the word-lines in the set.
3. The invention of claim 1 , wherein the first set of circuitry comprises, for each decoded bit (e.g., D 74 ) in the first subset:
a p-type transistor (e.g., 606 ) having its gate connected to receive the corresponding decoded bit and its channel connected between a high reference voltage (e.g., VDD) and the first node; and
an n-type transistor (e.g., 608 ) having its gate connected to receive the corresponding decoded bit and its channel connected between a low reference voltage (e.g., ground) and the first node.
4. The invention of claim 3 , wherein:
the first subset of decoded bits comprises at least two decoded bits (e.g., D 74 , D 118 );
the channels of the at least two p-type transistors (e.g., 602 , 606 ) associated with the decoded bits in the first subset are connected in parallel between the high reference voltage and the first node; and
the channels of the at least two n-type transistors (e.g., 604 , 608 ) associated with the decoded bits in the first subset are connected in series between the low reference voltage and the first node.
5. The invention of claim 4 , wherein the first set of circuitry further comprises:
another p-type transistor (e.g., 610 ) having its gate connected to receive an enable signal (e.g., EN) and having its channel connected in parallel with the channels of the at least two p-type transistors; and
another n-type transistor (e.g., 612 ) having its gate connected to receive the enable signal and having its channel connected in series with the channels of the at least two n-type transistors.
6. The invention of claim 1 , wherein the second set of circuitry comprises, for each decoded bit (e.g., D 0 ) in the second subset:
the corresponding feed-back latch (e.g., 622 , 626 , 628 ); and
a corresponding n-type transistor (e.g., 624 ) having its gate connected to receive the corresponding decoded bit and having its channel connected between the first node and the corresponding feed-back latch.
7. The invention of claim 6 , wherein each corresponding feed-back latch comprises:
a first p-type transistor (e.g., 622 ) having its gate connected to receive the corresponding decoded bit and having its channel connected between the high reference voltage and a second node (W 0 ) connected to the channel of the corresponding n-type transistor;
an inverter (e.g., 626 ) connected between the second node and an output node (e.g., WL 0 ) connected to the corresponding word-line; and
a second p-type transistor (e.g., 628 ) having its gate connected to the output node and having its channel connected in parallel with the channel of the first p-type transistor between the high reference voltage and the second node.
8. The invention of claim 1 , wherein, if a temporary noise glitch or decoded address overlap occurs in an unselected decoded bit in the second subset, then the corresponding feed-back latch inhibits the corresponding word-line from being energized.
9. The invention of claim 1 , wherein the word-line driver is part of an address decoder implemented in the integrated circuit.
10. The invention of claim 9 , wherein the address decoder is part of a memory device implemented in the integrated circuit.
11. The invention of claim 10 , wherein the integrated circuit is an FPGA.
12. The invention of claim 1 , wherein:
the first set of circuitry comprises, for each decoded bit (e.g., D 74 ) in the first subset:
a p-type transistor (e.g., 606 ) having its gate connected to receive the corresponding decoded bit and its channel connected between a high reference voltage (e.g., VDD) and the first node; and
an n-type transistor (e.g., 608 ) having its gate connected to receive the corresponding decoded bit and its channel connected between a low reference voltage (e.g., ground) and the first node;
the first set of circuitry is shared by all of the word-lines in the set; and
the second set of circuitry comprises, for each decoded bit (e.g., D 0 ) in the second subset:
the corresponding feed-back latch (e.g., 622 , 626 , 628 ); and
a corresponding n-type transistor (e.g., 624 ) having its gate connected to receive the corresponding decoded bit and having its channel connected between the first node and the corresponding feed-back latch.
13. The invention of claim 12 , wherein:
the first subset of decoded bits comprises at least two decoded bits (e.g., D 74 , D 118 );
the channels of the at least two p-type transistors (e.g., 602 , 606 ) associated with the decoded bits in the first subset are connected in parallel between the high reference voltage and the first node;
the channels of the at least two n-type transistors (e.g., 604 , 608 ) associated with the decoded bits in the first subset are connected in series between the low reference voltage and the first node; and
each corresponding feed-back latch comprises:
a first p-type transistor (e.g., 622 ) having its gate connected to receive the corresponding decoded bit and having its channel connected between the high reference voltage and a second node (W 0 ) connected to the channel of the corresponding n-type transistor;
an inverter (e.g., 626 ) connected between the second node and an output node (e.g., WL 0 ) connected to the corresponding word-line; and
a second p-type transistor (e.g., 628 ) having its gate connected to the output node and having its channel connected in parallel with the channel of the first p-type transistor between the high reference voltage and the second node.
14. The invention of claim 13 , wherein the first set of circuitry further comprises:
another p-type transistor (e.g., 610 ) having its gate connected to receive a distinct enable signal (e.g., EN) and having its channel connected in parallel with the channels of the at least two p-type transistors; and
another n-type transistor (e.g., 612 ) having its gate connected to receive the enable signal and having its channel connected in series with the channels of the at least two n-type transistors.
15. The invention of claim 13 , wherein, if a temporary noise glitch or decoded address overlap occurs in an unselected decoded bit in the second subset, then the corresponding feed-back latch inhibits the corresponding word-line from being energized.
16. The invention of claim 13 , wherein:
the word-line driver is part of an address decoder implemented in the integrated circuit; and
the address decoder is part of a memory device implemented in the integrated circuit.
17. An integrated circuit having an address decoder ( 100 ) comprising:
one or more bit decoders (e.g., 102 ), each adapted to convert one or more address bits (e.g., A 0 , A 1 ) into two or more decoded bits (e.g., DEC 0 –DEC 3 ); and
one or more word-line drivers (e.g., 104 , 600 ), each adapted to receive a set of decoded bits (e.g., D 0 , D 1 , D 74 , D 118 ) and control a set of word-lines (e.g., WL 0 , WL 1 ), each word-line driver comprising:
a first set of circuitry (e.g., 602 – 608 ) adapted to receive and process a first subset of one or more decoded bits (e.g., D 74 , D 118 ) and connected to a first node (e.g., W) in the word-line driver; and
a second set of circuitry (e.g., 614 – 628 ) connected to the first node and adapted to receive and process a second subset of decoded bits (e.g., D 0 , D 1 ) to control the set of word-lines, wherein, for each word-line (e.g., WL 0 ), the second set of circuitry comprises a corresponding feed-back latch (e.g., 622 , 626 , 628 ) controlled by a corresponding decoded bit (e.g., D 0 ) and adapted to drive the corresponding word-line low if the corresponding decoded bit indicates that the corresponding word-line is not selected.
18. The invention of claim 17 , wherein, if a temporary noise glitch or decoded address overlap occurs in an unselected decoded bit in the second subset, then the corresponding feed-back latch inhibits the corresponding word-line from being energized.
19. An integrated circuit having a memory device comprising:
a block of memory cells arranged in rows; and
an address decoder (e.g., 100 ) comprising:
one or more bit decoders (e.g., 102 ), each adapted to convert one or more address bits (e.g., A 0 , A 1 ) into two or more decoded bits (e.g., DEC 0 –DEC 3 ); and
one or more word-line drivers (e.g., 104 , 600 ), each adapted to receive a set of decoded bits (e.g., D 0 , D 1 , D 74 , D 118 ) and control a set of word-lines (e.g., WL 0 , WL 1 ) for the block of memory cells, each word-line driver comprising:
a first set of circuitry (e.g., 602 – 608 ) adapted to receive and process a first subset of one or more decoded bits (e.g., D 74 , D 118 ) and connected to a first node (e.g., W) in the word-line driver; and
a second set of circuitry (e.g., 614 – 628 ) connected to the first node and adapted to receive and process a second subset of decoded bits (e.g., D 0 , D 1 ) to control the set of word-lines, wherein, for each word-line (e.g., WL 0 ), the second set of circuitry comprises a corresponding feed-back latch (e.g., 622 , 626 , 628 ) controlled by a corresponding decoded bit (e.g., D 0 ) and adapted to drive the corresponding word-line low if the corresponding decoded bit indicates that the corresponding word-line is not selected.
20. The invention of claim 19 , wherein, if a temporary noise glitch or decoded address overlap occurs in an unselected decoded bit in the second subset, then the corresponding feed-back latch inhibits the corresponding word-line from being energized.