Reconfiguration of programmable logic devices
View Patent ↗Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks and corresponding input/output pins, and a plurality of configuration memory cells. The configuration memory cells are adapted to store configuration data for configuration of the logic blocks and the input/output blocks. A data port is adapted to provide a clock signal to and receive configuration data from an external memory. A plurality of circuits are adapted to hold the input/output pins in a known logic state during the configuration.
1. A programmable logic device comprising:
a plurality of logic blocks;
a plurality of input/output blocks and corresponding input/output pins, wherein the plurality of input/output pins are adapted to receive input data to store within the programmable logic device to provide a known state exit;
a plurality of configuration memory cells adapted to store configuration data for configuration of the logic blocks and the input/output blocks;
a data port adapted to provide a clock signal to and receive configuration data from an external memory; and
a plurality of circuits adapted to hold the input/output pins in a known logic state during the configuration.
2. The programmable logic device of claim 1 , wherein the data port is further adapted to load the configuration data to the configuration memory cells.
3. The programmable logic device of claim 1 , wherein each one of the circuits comprises a latch coupled to a pullup resistor and a pulldown resistor.
4. The programmable logic device of claim 1 , wherein the plurality of circuits comprises:
a plurality of bus keeper circuits; and
a plurality of boundary scan cells.
5. The programmable logic device of claim 1 , further comprising a soft IP core stored in the configuration memory cells and adapted to configure a JTAG port adapted to receive instructions for the circuits to hold the input/output pins in the known logic state.
6. The programmable logic device of claim 1 , further comprising a dedicated JTAG port adapted to receive instructions for the circuits to hold the input/output pins in the known logic state.
7. The programmable logic device of claim 1 , further comprising:
a plurality of registers within a logic area of the programmable logic device; and
an input path from at least one of the input/output pins to at least one of the registers to precondition the at least one of the registers with a desired signal value.
8. The programmable logic device of claim 1 , further comprising a plurality of registers, within a logic area of the programmable logic device, adapted to prevent glitches from being provided by the input/output blocks after the configuration.
9. The programmable logic device of claim 1 , wherein the external memory is a flash memory.
10. The programmable logic device of claim 1 , wherein the data port is configured as a serial peripheral interface (SPI) port.
11. A method of reconfiguring a programmable logic device, the method comprising:
triggering a reconfiguration of the programmable logic device while configuration memory cells of the programmable logic device are configured with configuration data;
capturing a plurality of output signal values of the programmable logic device;
providing a clock signal to an external non-volatile memory;
loading reconfiguration data into the configuration memory cells from the external non-volatile memory during the providing;
maintaining the output signal values during the loading; and
performing a known state exit operation for the programmable logic device.
12. The method of claim 11 , further comprising programming the external non-volatile memory with the reconfiguration data prior to the triggering.
13. The method of claim 11 , wherein the capturing is performed in response to a JTAG instruction.
14. The method of claim 11 , further comprising providing input data to the programmable logic device after the loading to precondition registers with the input data.
15. A system comprising:
a programmable logic device (PLD) having a plurality of configuration memory cells adapted to store configuration data;
means for storing, external to the programmable logic device, configuration data for configuring or reconfiguring the programmable logic device;
means for providing a clock signal from the programmable logic device to the storing means;
means for loading the configuration data into the configuration memory cells from the storing means based on the clock signal;
means for maintaining PLD output signal values during loading of the configuration data; and
means for capturing a plurality of output signal values of the programmable logic device.
16. The system of claim 15 , further comprising means for controlling the programmable logic device and the storing means for configuring or reconfiguring the programmable logic device.
17. The system of claim 15 , further comprising means for programming the configuration data into the storing means.