Selective programming of non-volatile memory facilitated by security fuses
View Patent ↗Methods and devices are disclosed herein to provide improved techniques for securing configuration data stored in non-volatile memories of programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a plurality of configuration data. A plurality of security fuses are adapted to store a plurality of logic states. Control logic is adapted to selectively secure the configuration data within the non-volatile memory based on the logic states stored in the plurality of security fuses.
1. A method of controlling the programming of non-volatile memory with configuration data in a programmable logic device, comprising:
storing in a plurality of programmable security fuses within the device a multiple bit security pattern;
comparing within the device multiple bits of the multiple bit security pattern with multiple bits of a predetermined multiple bit security pattern;
if the security patterns match, disabling programming of the non-volatile memory;
if the security patterns do not match, determining whether a test bit within the device has been enabled;
if the test bit is enabled, disabling programming of the non-volatile memory with the configuration data; and
if the test bit is not enabled, enabling programming of the non-volatile memory with the configuration data.
2. The method of claim 1 ,
wherein comparing within the device multiple bits of the multiple bit security pattern with multiple bits of a predetermined multiple bit security pattern comprises comparing one portion of the stored multiple bit security pattern with another portion.
3. The method of claim 1 ,
wherein comparing within the device multiple bits of the multiple bit security pattern with multiple bits of a predetermined multiple bit security pattern comprises comparing a predetermined multiple bit security pattern hardwired into the control logic with the stored multiple bit security pattern.
4. The method of claim 1 , wherein the security fuses are memory cells of the non-volatile memory.
5. The method of claim 1 , wherein the security fuses are one-time programmable (OTP) fuses.
6. The method of claim 1 , wherein the non-volatile memory is flash memory.
7. The method of claim 1 , wherein the predetermined multiple bit security pattern is not a bulk erased pattern, a bulk programmed pattern, a checkerboard pattern, or a checkerboard-bar pattern.
8. A programmable logic device comprising:
programmable non-volatile memory for storing configuration data for the device;
a plurality of programmable security fuses for storing a multiple bit security pattern; and
control logic operable for:
comparing within the device multiple bits of the multiple bit security pattern with multiple bits of a predetermined multiple bit security pattern;
if the security patterns match, disabling programming of the non-volatile memory;
if the security patterns do not match, determining whether a test bit within the device has been enabled;
if the test bit is enabled, disabling programming of the non-volatile memory with the configuration data; and
if the test bit is not enabled, enabling programming of the non-volatile memory with the configuration data.
9. The programmable logic device of claim 8 , wherein, in comparing a multiple bit security pattern stored in the security fuses with a predetermined multiple bit security pattern, the control logic is operable for compare to portion of the stored multiple bit security pattern with another portion.
10. The programmable logic device of claim 8 , wherein, in comparing a multiple bit security pattern stored in the security fuses with a predetermined multiple bit security pattern, the control logic is operable to compare a predetermined multiple bit security pattern hardwired into the control logic with the stored multiple bit security pattern.
11. The programmable logic device of claim 8 , wherein the control logic comprises:
decode logic for comparing the stored multiple bit security pattern with the predetermined multiple bit security pattern; and
an OR gate coupled at its inputs to the output of the decode logic and to a signal path for receiving the test signal, the output of the OR gate operable to provide a control signal for enabling or disabling programming of the non-volatile memory.
12. The programmable logic device of claim 8 , wherein the security fuses are memory cells of the non-volatile memory.
13. The programmable logic device of claim 8 , wherein the security fuses are one-time programmable (OTP) fuses.
14. The programmable logic device of claim 8 , wherein the non-volatile memory is flash memory.
15. The programmable logic device of claim 8 , wherein the predetermined multiple bit security pattern is not a bulk erased pattern, a bulk programmed pattern, a checkerboard pattern, or a checkerboard-bar pattern.
16. A programmable logic device comprising:
programmable non-volatile memory for storing configuration data for the device;
a plurality of programmable security fuses for storing a multiple bit security pattern; and
means for:
comparing within the device multiple bits of the multiple bit security pattern with multiple bits of a predetermined multiple bit security pattern;
if the security patterns match, disabling programming of the non-volatile memory;
if the security patterns do not match, determining whether a test bit within the device has been enabled;
if the test bit is enabled, disabling programming of the non-volatile memory with the configuration data; and
if the test bit is not enabled, enabling programming of the non-volatile memory with the configuration data.