IP Library Granted Patent US 7,547,995
Granted Patent B1
US 7,547,995 · App. 11/345,713 · Granted Jun 16, 2009

Dynamic over-voltage protection scheme for interface circuitry

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Quick Facts
Patent No.
US 7,547,995
App. No.
11/345,713
Granted
Jun 16, 2009
Kind
B1
Abstract

In one embodiment of the invention, an integrated device has interface circuitry that includes a dynamic monitor that monitors the relative potential between (at least) two different power supplies to enable the device to react to over-voltage conditions such that appropriate selections can be made for which power supplies are selected for different components in the interface circuitry, such as output drivers and input receivers. The dynamic monitor enables over-voltage protection to be automatically implemented before the device has been configured, such as during the device's power-on state.

Claims (36)

1. An integrated device having an interface circuit comprising:

a monitor adapted to dynamically compare first and second power supplies in order to generate a dynamic control signal; and

at least one switch module adapted to select, based on the dynamic control signal, one of the first and second power supplies for use in powering at least one input/output (I/O) component of the interface circuit, wherein the monitor comprises:

a bias circuit adapted to generate a reduced switch-point voltage level based on the second power supply;

a dynamic comparator adapted to compare the switch-point voltage level to the first power supply to generate at least one intermediate control signal indicative of whether the first power supply is greater than the second power supply by a predetermined amount;

a signal driver adapted to generate an other intermediate control signal based on the at least one intermediate control signal, wherein the dynamic control signal is generated based on the other intermediate control signal; and

a mux adapted to generate the dynamic control signal based on either the other intermediate control signal or a configuration setting, wherein:

the mux selects the other intermediate control signal before configuration of the integrated device is complete; and

the mux selects the configuration setting after the configuration of the integrated device is complete.

2. The invention of claim 1 , wherein the monitor and the at least one switch module are adapted to protect the at least one I/O component from the over-voltage condition prior to the integrated device being completely configured.

3. The invention of claim 2 , wherein:

the interface circuit is a programmable interface circuit; and

the monitor and the at least one switch module are adapted to protect the at least one I/O component from the over-voltage condition prior to the programmable interface circuit being programmed.

4. The invention of claim 1 , wherein:

the at least one I/O component comprises an output driver;

if the level of the first power supply is greater than the level of the second power supply by a predetermined amount, then the monitor generates the dynamic control signal to control the switch module to select the second power supply for use in powering the output driver; and

if the level of the first power supply is not greater than the level of the second power supply by the predetermined amount, then the monitor generates the dynamic control signal to control the switch module to select the first power supply for use in powering the output driver.

5. The invention of claim 1 , wherein:

the at least one I/O component comprises an input receiver;

if the level of the first power supply is greater than the level of the second power supply by a predetermined amount, then the monitor generates the dynamic control signal to control the switch module to select the first power supply for use in powering the input receiver; and

if the level of the first power supply is not greater than the level of the second power supply by the predetermined amount, then the monitor generates the dynamic control signal to control the switch module to select the second power supply for use in powering the input receiver.

6. The invention of claim 1 , wherein:

the interface circuit has a single monitor and a plurality of I/O buffers; and

the single monitor and the at least one switch module control selection of power supplies for use in powering at least one I/O component in each of the I/O buffers.

7. The invention of claim 1 , wherein the monitor comprises:

a bias circuit adapted to generate a reduced switch-point voltage level based on the second power supply;

a dynamic comparator adapted to compare the switch-point voltage level to the first power supply to generate at least one intermediate control signal indicative of whether the first power supply is greater than the second power supply by a predetermined amount; and

a signal driver adapted to generate an other intermediate control signal based on the at least one intermediate control signal, wherein the dynamic control signal is generated based on the other intermediate control signal.

8. The invention of claim 7 , wherein:

a logic-high state of the at least one intermediate control signal is based on the first power supply; and

the signal driver is adapted to perform level-shifting such that a logic-high state of the other configuration control signal is based on the second power supply.

9. The invention of claim 1 , wherein:

the interface circuit is a programmable interface circuit;

the monitor is adapted to generate the dynamic control signal to control the at least one switch module to select a power supply that protects the at least one I/O component from an over-voltage condition prior to the programmable interface circuit being programmed;

the interface circuit has a single monitor and a plurality of I/O buffers; and

the single monitor and the at least one switch module control selection of power supplies for use in powering at least one I/O component in each of the I/O buffers.

Assignments (3)
SECURITY INTEREST Recorded May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
SECURITY INTEREST Recorded Mar 18, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035223/0001 →