Patent Assignment
Reel/Frame 046099/0269
Assignment of Assignor's Interest
Recorded: 2018-05-04
Pages: 28
Assignor
KILOPASS TECHNOLOGY, INC.
Executed: 2018-05-01
Assignee
SYNOPSYS, INC.
690 EAST MIDDLEFIELD ROAD, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties
(63)
Semiconductor Memory Cell and Memory Array Using a Breakdown Phenomena in an Ultra-Thin Dielectric
PCT:
PCT/US2002/029507 ↗
Smart Card Having Memory Using a Breakdown Phenomena in an Ultra-Thin Dielectric
PCT:
PCT/US2002/033049 ↗
Reprogrammable Non-Volatile Memory Using a Breakdown Phenomena in an Ultra-Thin Dielectric
PCT:
PCT/US2002/033172 ↗
Method of Testing the Thin Oxide of a Semiconductor Memory Cell That Uses Breakdown Voltage
PCT:
PCT/US2004/005336 ↗
Electrically Programmable Fuse Bit
PCT:
PCT/US2007/061233 ↗
Cross-Coupled Thyristor Sram Semiconductor Structures and Methods of Fabrication
PCT:
PCT/US2015/052468 ↗
Cross-Coupled Thyristor Sram Semiconductor Structures and Methods of Fabrication
PCT:
PCT/US2015/052480 ↗
Two-Transistor Sram Semiconductor Structure and Methods of Fabrication
PCT:
PCT/US2015/052488 ↗
Six-Transistor Sram Semiconductor Structures and Methods of Fabrication
PCT:
PCT/US2015/052493 ↗
Write Assist Sram Circuits and Methods of Operation
PCT:
PCT/US2015/052497 ↗
Thyristor Volatile Random Access Memory and Methods of Manufacture
PCT:
PCT/US2015/052499 ↗
Methods of Retaining and Refreshing Data a Thyristor Random Access Memory
PCT:
PCT/US2015/052505 ↗
Power Reduction in Thyristor Random Access Memory
PCT:
PCT/US2015/052507 ↗
Mtp-Thyristor Memory Cell Circuits and Methods of Operation
PCT:
PCT/US2016/018121 ↗
Semiconductor Memory Cell and Memory Array Using a Breakdown Phenomena in an Ultra-Thin Dielectric
Smart Card Having Memory Using a Breakdown Phenomena in an Ultra-Thin Dielectric
Reprogrammable Non-Volatile Memory Using a Breakdown Phenomena in an Ultra-Thin Dielectric
Semiconductor Memory Cell and Memory Array Using a Breakdown Phenomena in an Ultra-Thin Dielectric
High Density Semiconductor Memory Cell and Memory Array Using a Single Transistor
Programming Methods and Circuits for Semiconductor Memory Cell and Memory Array Using a Breakdown Phenomena in an Ultra-Thin Dielectric
Reprogrammable Non-Volatile Memory Using a Breakdown Phenomena in an Ultra-Thin Dielectric
Method of Testing the Thin Oxide of a Semiconductor Memory Cell That Uses Breakdown Voltage
Patent:
6,791,891 →
Application:
10/406,406 →
High Density Semiconductor Memory Cell and Memory Array Using a Single Transistor
Semiconductor Memory Cell and Memory Array Using a Breakdown Phenomena in an Ultra-Thin Dielectric
Field Programmable Gate Array
High Density Semiconductor Memory Cell and Memory Array Using a Single Transistor Having a Buried N+ Connection
High Density Semiconductor Memory Cell and Memory Array Using a Single Transistor and Having Variable Gate Oxide Breakdown
Combination Field Programmable Gate Array Allowing Dynamic Reprogrammability and Non-Volatile Programmability Based Upon Transistor Gate Oxide Breakdown
Methods and Circuits for Testing Programmability of a Semiconductor Memory Cell and Memory Array Using a Breakdown Phenomenon in an Ultra-Thin Dielectric
High Density Semiconductor Memory Cell and Memory Array Using a Single Transistor and Having Counter-Doped Poly and Buried Diffusion Wordline
Combination Field Programmable Gate Array Allowing Dynamic Reprogrammability
Methods and Circuits for Programming of a Semiconductor Memory Cell and Memory Array Using a Breakdown Phenomenon in an Ultra-Thin Dielectric
Field Programmable Gate Array
Field Programmable Gate Array
3.5 Transistor Non-Volatile Memory Cell Using Gate Breakdown Phenomena
Patent:
7,173,851 →
Application:
11/252,461 →
Memory Transistor Gate Oxide Stress Release and Improved Reliability
Non-Volatile Semiconductor Memory Based on Enhanced Gate Oxide Breakdown
Electrically Programmable Fuse Bit
Memory Transistor Gate Oxide Stress Release and Improved Reliability
Reducing Bit Line Leakage Current in Non-Volatile Memories
Method and Apparatus for Programming Auto Shut-Off
Non-Volatile Semiconductor Memory Based on Enhanced Gate Oxide Breakdown
Electrically Programmable Fuse Bit
One-Time Programmable Memory
One-Time Programmable Memory and Method for Making the Same
One-Time Programmable Memory and Method for Making the Same
One-Time Programmable Memory and Method for Making the Same
Thyristor Volatile Random Access Memory and Methods of Manufacture
Application:
14/841,140 →
Publication:
US 2016/0093624
Reduced Power Read Sensing for One-Time Programmable Memories
Write Enhancement for One Time Programmable (OTP) Semiconductors
Semiconductor Memory Sensing Architecture
One-Time Programmable Memory and Method for Making the Same
Cmos Low Voltage Bandgap Reference Design with Orthogonal Output Voltage Trimming
Patent:
9,696,744 →
Application:
15/281,054 →
Protection Circuit for Integrated Circuit Die-Let After Scribe Cut
High-Speed Differential Current Sensing of Preprogrammed NVM Cells
Circuit for Low-Dropout Regulator Output
MTP-Thyristor Memory Cell Circuits and Methods of Operation
Voltage Reference Circuits with Programmable Temperature Slope and Independent Offset Control
Tunable Sense Amplifier Reference for Single-Ended Bit Lines
Patent:
9,754,641 →
Application:
15/354,397 →
Three-Transistor Otp Memory Cell
Gate Oxide Breakdown in OTP Memory Cells for Physical Unclonable Function (PUF) Security
Low Power Voltage Level Shifter Circuit
Patent:
10,103,732 →
Application:
15/724,861 →
OTP Cell with Improved Programmability
Patent:
10,163,520 →
Application:
15/785,364 →
Related Assignments
(10)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Mar 6, 2015
From: LATTICE SEMICONDUCTOR LIMITED
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 035101/0559 →
Security Interest
Mar 18, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035222/0866 →
Corrective Assignment to Correct the Assignee Name Previously Recorded at Reel: 012877 Frame: 0804. Assignor(S) Hereby Confirms the Assignment.
Aug 29, 2016
From: PENG, JACK ZEZHONG
To: KILOPASS TECHNOLOGY, INC.
Reel/Frame 040365/0509 →
Corrective Assignment to Correct the Assignee Name Previously Recorded at Reel: 012877 Frame: 0796. Assignor(S) Hereby Confirms the Assignment.
Aug 29, 2016
From: PENG, JACK ZEZHONG
To: KILOPASS TECHNOLOGY, INC.
Reel/Frame 040365/0874 →
Assignment of Assignor's Interest
Aug 29, 2016
From: PENG, JACK ZEZHONG
To: KILOPASS TECHNOLOGY, INC.
Reel/Frame 040367/0258 →
Assignment of Assignor's Interest
Aug 29, 2016
From: PENG, JACK ZEZHONG
To: KILOPASS TECHNOLOGY, INC.
Reel/Frame 040367/0331 →
Security Interest
Aug 30, 2016
From: KILOPASS TECHNOLOGY, INC.
To: STRUCTURAL CAPITAL INVESTMENTS II, LP
Reel/Frame 039884/0004 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Assignment of Assignor's Interest
Dec 13, 2019
From: KILOPASS TECHNOLOGY, INC.
To: SYNOPSYS, INC.
Reel/Frame 051271/0052 →