Patent Assignment
Reel/Frame 035222/0866
Security Interest
Recorded: 2015-03-18
Pages: 83
Assignors
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2015-03-10
SIBEAM, INC.
Executed: 2015-03-10
SILICON IMAGE, INC.
Executed: 2015-03-10
DVDO, INC.
Executed: 2015-03-10
Assignee
JEFFERIES FINANCE LLC
520 MADISON AVENUE, NEW YORK, NEW YORK, 10022
Covered Properties
(100)
Fifo Memory with Programmable Data Port Widths
Patent:
6,986,004 →
Application:
10/409,543 →
Programmable Logic Device Architecture Based on Arrays of Lut-Based Boolean Terms
Patent:
6,879,184 →
Application:
10/417,290 →
Programmable and Fixed Logic Circuitry for High-Speed Interfaces
Patent:
6,894,530 →
Application:
10/425,862 →
Scalable Device Architecture for High-Speed Interfaces
Patent:
6,903,575 →
Application:
10/425,863 →
Cascaded Logic Block Architecture for Complex Programmable Logic Devices
Patent:
6,861,871 →
Application:
10/428,885 →
Multi-Stage Interconnect Architecture for Complex Programmable Logic Devices
Patent:
6,864,713 →
Application:
10/428,888 →
Cpld with Multi-Function Blocks and Distributed Memory
Patent:
6,879,182 →
Application:
10/428,889 →
Programmable Logic Device with Enhanced Wide and Deep Logic Capability
Patent:
6,922,078 →
Application:
10/428,982 →
Non-Volatile and Reconfigurable Programmable Logic Devices
Patent:
6,828,823 →
Application:
10/439,602 →
Measuring Propagation Delays of Programmable Logic Devices
Patent:
7,039,842 →
Application:
10/441,814 →
Skew Cancellation for Source Synchronous Clock and Data Signals
Patent:
7,301,996 →
Application:
10/447,120 →
Digitally Controlled Delay Cells
Integrated Circuit Including External Electronic Components with Low Insertion Loss
Patent:
7,304,863 →
Application:
10/457,630 →
Flexible Media Access Control Architecture
Synchronization of Programmable Multiplexers and Demultiplexers
Patent:
6,856,171 →
Application:
10/460,385 →
High Speed Interface for a Programmable Interconnect Circuit
Patent:
6,861,868 →
Application:
10/463,781 →
Bi-Directional Buffering for Memory Data Lines
Integrated Circuit and Associated Design Method Using Spare Gate Islands
Patent:
6,822,477 →
Application:
10/600,042 →
High-Performance Non-Volatile Memory Device and Fabrication Process
Patent:
6,977,408 →
Application:
10/610,253 →
Noise-Shielding, Switch-Controlled Load Circuitry for Oscillators and the Like
Patent:
7,132,903 →
Application:
10/613,460 →
Programmable I/O Interfaces for Fpgas and Other Plds
Patent:
6,952,115 →
Application:
10/613,462 →
Programmable Logic Device with Hardwired Microsequencer
Patent:
6,958,625 →
Application:
10/617,980 →
Scalable Serializer-Deserializer Architecture and Programmable Interface
Patent:
7,098,685 →
Application:
10/619,645 →
Programmable Logic Device with Enhanced Wide Input Product Term Cascading
Patent:
6,903,573 →
Application:
10/619,711 →
Algorithm to Increase Logic Input Width by Cascading Product Terms
Patent:
7,032,203 →
Application:
10/620,147 →
Field Programmable Gate Array Having Embedded Memory with Configurable Depth and Width
Patent:
6,919,736 →
Application:
10/620,286 →
Programmable Logic Device with a Memory-Based Finite State Machine
Patent:
6,940,309 →
Application:
10/624,965 →
Zero Power Memory Cell with Reduced Threshold Voltage
Patent:
6,737,702 →
Application:
10/626,089 →
Programmable Lock Detector and Corrector
Patent:
6,970,047 →
Application:
10/628,656 →
Programmable Signal Termination for Fpgas and the Like
Patent:
6,924,659 →
Application:
10/628,657 →
Clock Generator with Skew Control
Clock Generator
Memory Access via Serial Memory Interface
Integrated Circuit and Associated Design Method with Antenna Error Control Using Spare Gates
Patent:
6,877,667 →
Application:
10/640,804 →
Enhanced Cpld Macrocell Module Having Selectable Bypass of Steering-Based Resource Allocation
Patent:
6,838,904 →
Application:
10/640,828 →
Programmable Broadcast Initialization of Memory Blocks
Field Programmable Gate Array
Shared Transmission Line Communication System and Method
Patent:
6,842,037 →
Application:
10/655,686 →
Delay-Matched Asic Conversion of a Programmable Logic Device
Patent:
7,038,490 →
Application:
10/660,814 →
Controlled Hysteresis Comparator with Rail-to-Rail Input
Patent:
6,970,022 →
Application:
10/665,920 →
Programmable I/O Structure for Fpgas and the Like Having Shared Circuitry
Patent:
6,943,582 →
Application:
10/671,363 →
Programmable I/O Structure for Fpgas and the Like Having Reduced Pad Capacitance
Patent:
6,943,583 →
Application:
10/671,378 →
Multiport Memory with Twisted Bitlines
Patent:
6,909,663 →
Application:
10/671,756 →
Semiconductor Device Adapted for Forming Multiple Scan Chains
Patent:
7,269,771 →
Application:
10/676,536 →
Analog-To-Digital Converters
Patent:
6,809,674 →
Application:
10/687,468 →
Lateral High-Voltage Junction Device
Clock Generation
Patent:
7,091,763 →
Application:
10/701,005 →
Programmable Logic Device with Flexible Memory Allocation and Routing
Patent:
7,088,134 →
Application:
10/704,025 →
Programmable Power Management System and Method
Patent:
7,100,058 →
Application:
10/726,972 →
Power Supply Remote Voltage Sensing
Patent:
7,187,157 →
Application:
10/728,685 →
Linear Thermoelectric Device Driver
Patent:
6,981,381 →
Application:
10/737,514 →
Method for Configuring Multiple-Output Phase-Locked Loop Frequency Synthesizer
Patent:
7,132,864 →
Application:
10/744,353 →
Output Stages for High Current Low Noise Bandgap Reference Circuit Implementations
Electrostatic Discharge Simulation
Combination Field Programmable Gate Array Allowing Dynamic Reprogrammability and Non-Volatile Programmability Based Upon Transistor Gate Oxide Breakdown
Upgradeable and Reconfigurable Programmable Logic Device
Fast Diagonal Interleaved Parity (Dip) Calculator
Patent:
7,191,388 →
Application:
10/791,073 →
Timer Systems and Methods
Powering-Up a Device Having Digital and Analog Circuitry
Systems and Methods for Controlling Voltage Regulator Module Power Supplies
Sense Amplifier Systems and Methods
Table-Based Scheduler for Fifos and the Like
Patent:
7,234,030 →
Application:
10/809,180 →
Configuring Fpgas and the Like Using One or More Serial Memory Devices
Patent:
7,095,247 →
Application:
10/809,658 →
Self-Adjusting Schmitt Trigger
Patent:
7,167,032 →
Application:
10/815,403 →
Charge Pump for a Low-Voltage Wide-Tuning Range Phase-Locked Loop
Dynamic Gain Adjustment Systems and Methods for Metastability Resistance
Patent:
6,998,896 →
Application:
10/829,865 →
Low Pass Filter Systems and Methods
Patent:
6,998,906 →
Application:
10/834,528 →
High-Voltage Protection Device and Process
Patent:
7,307,319 →
Application:
10/837,086 →
Switched Capacitor Ripple-Smoothing Filter
Control Signal Generation for a Low Jitter Switched-Capacitor Frequency Synthesizer
I/O Buffer Architecture for Programmable Devices
Patent:
7,061,269 →
Application:
10/843,708 →
Current Mode Logic Buffer
Combination Field Programmable Gate Array Allowing Dynamic Reprogrammability
Memory Systems and Methods
Byte Enable Logic for Memory
Data Transmission Synchronization
Process for Fabricating a Semiconductor Device Having Electrically Isolated Low Voltage and High Voltage Regions
Patent:
7,078,286 →
Application:
10/928,563 →
Testing Embedded Memory in an Integrated Circuit
Field Programmable Gate Arrays Using Both Volatile and Nonvolatile Memory Cell Properties and Their Control
Memory Output Data Systems and Methods with Feedback
Field Programmable Gate Array Logic Unit and Its Cluster
Programmable Logic Device Having a Configurable Dram with Transparent Refresh
Patent:
7,129,749 →
Application:
10/974,305 →
Variable Data Width Memory Systems and Methods
Patent:
7,307,912 →
Application:
10/974,453 →
Testing Embedded Memory in Integrated Circuits Such as Programmable Logic Circuit
Patent:
7,376,872 →
Application:
10/978,899 →
Low Power Asynchronous Sense Amp
Patent:
7,161,862 →
Application:
10/996,283 →
Dynamic Over-Voltage Protection Scheme for Integrated-Circuit Devices
Patent:
7,230,810 →
Application:
11/007,954 →
Programmable Current Output Buffer
Patent:
7,215,148 →
Application:
11/012,548 →
Interface Circuitry for Electrical Systems
Patent:
7,215,149 →
Application:
11/012,550 →
Initializing Memory Blocks
Patent:
7,177,221 →
Application:
11/015,265 →
Sense Amplifier Timing
Patent:
7,177,207 →
Application:
11/015,369 →
Cascadable Memory
Patent:
7,187,203 →
Application:
11/016,665 →
Self-Verification of Configuration Memory in Programmable Logic Devices
Patent:
7,257,750 →
Application:
11/036,630 →
Eeprom Device with Voltage-Limiting Charge Pump Circuit
Patent:
7,242,053 →
Application:
11/036,738 →
Serdes with Programmable I/O Architecture
Patent:
7,208,975 →
Application:
11/040,772 →
Synchronous Memory
Patent:
7,183,798 →
Application:
11/041,319 →
Synchronization of Programmable Multiplexers and Demultiplexers
Patent:
7,109,754 →
Application:
11/044,089 →
Synchronization of Programmable Multiplexers and Demultiplexers
Patent:
7,109,756 →
Application:
11/044,149 →
Clock Generator with Skew Control
Patent:
7,034,599 →
Application:
11/044,508 →
Multi-Port Memory Systems and Methods for Bit Line Coupling
Patent:
7,221,607 →
Application:
11/054,011 →
Programmable Logic Devices with Integrated Standard-Cell Logic Blocks
Patent:
6,975,137 →
Application:
11/055,280 →
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Release of Security Interest
Oct 30, 2015
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 037018/0479 →
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →