Synchronization of programmable multiplexers and demultiplexers
View Patent ↗Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output circuitry. In accordance with another embodiment, a clock divider along with an edge clock distribution scheme is employed to distribute clock and reset signals for input/output circuitry.
1. A programmable logic device comprising:
a feedback circuit adapted to synchronize a first clock signal and a second clock signal; and
an input/output circuit coupled to the feedback circuit and adapted to receive the first and second clock signals and a reset signal to generate a local synchronization signal.
2. The programmable logic device of claim 1 , wherein the reset signal is a first reset signal and the feedback circuit is further adapted to synchronize the first reset signal to the second clock signal to generate a second reset signal, the second reset signal synchronized to the first clock signal to generate the local synchronization signal.
3. The programmable logic device of claim 1 , wherein the feedback circuit comprises a phase-locked loop circuit or a delay-locked loop circuit.
4. The programmable logic device of claim 2 , wherein the input/output circuit comprises:
a first flip flop which receives the first reset signal and is clocked by the second clock signal to generate a first output signal;
a second flip flop which receives the first output signal and is clocked by the second clock signal to generate the second reset signal; and
a third flip flop which receives the second reset signal and is clocked by the first clock signal to generate the local synchronization signal.
5. The programmable logic device of claim 4 , further comprising a delay element, coupled between the second flip flop and the third flip flop, adapted to delay the second reset signal.
6. The programmable logic device of claim 5 , wherein the delay is programmable to maintain required setup and hold times.
7. The programmable logic device of claim 1 , wherein the local synchronization signal is synchronized to the same clock cycle of the first clock signal.
8. A method of synchronizing a plurality of input/output circuits on a programmable logic device, the method comprising:
synchronizing a first clock signal to a second clock signal;
transmitting the first and second clock signals and a first reset signal to the plurality of input/output circuits;
synchronizing the first reset signal to the second clock signal to generate a second reset signal; and
synchronizing the second reset signal to the first clock signal to generate a local synchronization signal.
9. The method of claim 8 , wherein the local synchronization signal for each of the plurality of input/output circuits is synchronized to the same clock cycle of the first clock signal.
10. The method of claim 8 , further comprising delaying the second reset signal prior to synchronizing the second reset signal to the first clock signal.
11. The method of claim 10 , wherein the delaying is programmable to maintain required setup and hold times.
12. A programmable logic device comprising:
a clock generator circuit adapted to receive a high-speed clock signal and to produce a low-speed clock signal synchronized to the high-speed clock signal;
a plurality of input/output circuits coupled to the clock generation circuit, each adapted to receive the high-speed clock signal, the low-speed clock signal, and a reset signal and to generate therefrom a synchronization signal for synchronizing multiplexers and demultiplexers within the input/output circuit.
13. The programmable logic device of claim 12 , wherein the clock generator circuit comprises a phase-locked loop circuit or a delay-locked loop circuit.