Data transmission synchronization

1. An integrated circuit comprising:

a synchronization circuit adapted to receive a first clock signal and a synchronization signal and provide at least a second clock signal and a third clock signal;

a first divider circuit adapted to receive the second clock signal and provide a first divided clock signal;

a second divider adapted to receive the third clock signal and the first divided clock signal and provide a second divided clock signal;

at least two multiplexers adapted to receive the second divided clock signal and an input signal, which provides a number of parallel bits, and selectively provide the parallel bits under control of the second divided clock signal; and

an output multiplexer adapted to receive the first divided clock signal and the parallel bits from the at least two multiplexers and provide a serial output signal based on the input signal.

2. The integrated circuit of claim 1 , wherein the at least two multiplexers comprises two multiplexers, each receiving half of the parallel bits of the input signal.

3. The integrated circuit of claim 1 , further comprising a reference circuit having a phase locked loop circuit, wherein the reference circuit is adapted to receive a reference clock signal and provide the first clock signal and the synchronization signal.

4. The integrated circuit of claim 1 , wherein the synchronization circuit is further adapted to provide a fourth clock signal, with the first divider circuit adapted to receive the fourth clock signal.

5. The integrated circuit of claim 1 , wherein the synchronization circuit, the first and second divider circuit, the at least two multiplexers, and the output multiplexer comprise a serializer circuit, the integrated circuit further comprising a plurality of the serializer circuits having corresponding serial output signals for corresponding communication channels.

6. The integrated circuit of claim 5 , wherein the serial output signals for the serializer circuits are synchronized across the communication channels.

7. The integrated circuit of claim 5 , wherein the serial output signals for the serializer circuits are synchronized across the communication channels with corresponding ones of the parallel bits for each of the serial output signals transmitted at approximately the same time.

8. The integrated circuit of claim 1 , wherein the synchronization circuit, the first and second divider circuit, the at least two multiplexers, and the output multiplexer comprise a serializer circuit to provide parallel to serial conversion, the integrated circuit further comprising a number of the serializer circuits which are synchronized based upon the synchronization signal.

9. A circuit comprising:

a synchronization circuit adapted to receive a synchronization signal and provide at least a first clock signal;

a divider circuit adapted to receive the at least first clock signal and provide at least a first divided down clock signal; and

a multiplexer circuit adapted to receive the at least first divided down clock signal and an input signal, providing a number of parallel bits, and selectively provide from among the parallel bits a serial output signal based on the input signal and under control of the at least first divided down clock signal;

wherein the multiplexer circuit comprises a first and a second multiplexer, each receiving half of the parallel bits of the input signal and the first divided down clock signal, and a third multiplexer coupled to the first and second multiplexer and receiving the second divided down clock signal, the third multiplexer receiving output signals from the first and second multiplexer and providing the serial output signal; and

wherein the synchronization circuit, the divider circuit, and the multiplexer circuit comprise a serializer circuit, the circuit further comprising a number of the serializer circuits, which are synchronized based upon the synchronization signal.

10. The circuit of claim 9 , further comprising a reference circuit adapted to receive a reference clock signal and provide the synchronization signal to the synchronization circuit.

11. The circuit of claim 9 , wherein the serializer circuits provide corresponding ones of the parallel bits in a synchronized fashion via the serial output signals of the multiplexer circuits.

12. The circuit of claim 9 , wherein each of the synchronization circuits is further adapted to receive a clock signal, which is provided in a uniform fashion within the corresponding serializer circuit.

13. The circuit of claim 9 , wherein the at least first clock signal comprises a first, a second, and a third clock signal.

14. The circuit of claim 9 , wherein the divider circuit comprises a first divider circuit providing the first divided down clock signal, and a second divider circuit providing a second divided down clock signal.

15. A method for providing parallel to serial data conversion and data transmission synchronization across a number of communication channels, the method comprising:

providing a synchronous signal and a clock signal that are synchronized across the communication channels;

generating a first divided down clock signal based on the synchronous signal and the clock signal for each of the communication channels;

generating a second divided down clock signal based on the synchronous signal and the clock signal for each of the communication channels; and

multiplexing parallel input data bits into serial data bits under control of the first divided down clock signal and the second divided down clock signal, wherein the serial data bits are synchronized across the communication channels.

16. The method of claim 15 , further comprising:

providing a reference clock signal; and

generating the synchronous signal and the clock signal based on the reference clock signal.

17. The method of claim 15 , wherein the parallel input data bits for each of the communication channels are transmitted synchronously through the communication channels.