Sense amplifier timing
View Patent ↗Systems and methods provide sense amplifier timing techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of memory cells and a sense amplifier that provides a sense amplifier output signal based on data provided by the plurality of memory cells, with the sense amplifier output signal provided under control of a sense amplifier enable signal. A delay control circuit provides a delay to the sense amplifier enable signal based on a value provided by at least one configuration fuse.
1. An integrated circuit comprising:
a plurality of memory cells;
a sense amplifier adapted to provide a sense amplifier output signal based on data provided by the plurality of memory cells, wherein the sense amplifier output signal is provided under control of a sense amplifier enable signal;
at least one configuration fuse, wherein the at least one configuration fuse comprises programmable static random access memory adapted to store and provide a value having logical high and logical low signal levels based on the programming;
configuration memory adapted to configure the integrated circuit;
a configuration circuit adapted to configure the at least one configuration fuse and the configuration memory; and
a delay control circuit adapted to provide a delay to the sense amplifier enable signal based on the value provided by the at least one configuration fuse.
2. The integrated circuit of claim 1 , wherein the delay control circuit comprises:
a plurality of delay elements providing corresponding delayed versions of an enable signal; and
a multiplexer, wherein the multiplexer is controlled based on the value provided by the at least one configuration fuse to select from among the delayed versions of the enable signal to provide as the sense amplifier enable signal.
3. The integrated circuit of claim 1 , further comprising logic circuits adapted to be configured to provide user-defined functions.
4. The integrated circuit of claim 1 , wherein the at least one configuration fuse comprises four configuration fuses adapted to provide four control signals to the delay control circuit.
5. The integrated circuit of claim 1 , further comprising a decoder adapted to receive the value provided by the at least one configuration fuse and provide the decoded value to the delay control circuit to control the delay applied to the sense amplifier enable signal.
6. The integrated circuit of claim 1 , wherein the integrated circuit comprises a programmable logic device, wherein the at least one configuration fuse is formed as part of the configuration memory.
7. A programmable logic device comprising:
a block of memory having a plurality of columns of memory cells and a corresponding plurality of sense amplifiers adapted to provide sense amplifier output signals based on information stored in the block of memory;
at least one fuse adapted to provide a delay control output signal, wherein the at least one fuse comprises programmable static random access memory adapted to store and provide a value having logical high and logical low signal levels based on the programming;
configuration memory adapted to configure the programmable logic device;
a configuration circuit adapted to configure the at least one fuse and the configuration memory; and
a delay control circuit adapted to selectively determine when the sense amplifier output signals are provided based on the delay control output signal provided by the at least one fuse.
8. The programmable logic device of claim 7 , further comprising a plurality of the blocks of memory and a corresponding plurality of the delay control circuits.
9. The programmable logic device of claim 7 , wherein the delay control circuit comprises:
a plurality of different, selectable delay paths for a sense amplifier enable signal that controls when the sense amplifier output signals are provided from the sense amplifiers; and
a multiplexer adapted to select the desired delay path for the sense amplifier enable signal based on the delay control output signal.
10. The programmable logic device of claim 7 , wherein the block of memory further comprises a memory interface adapted to interface with the configuration circuit.
11. The programmable logic-device of claim 7 , further comprising logic circuits adapted to be configured to provide user-defined functions.
12. The programmable logic device of claim 7 , wherein the at least one fuse comprises four fuses adapted to provide four control signals to the delay control circuit.
13. The programmable logic device of claim 7 , further comprising a decoder adapted to receive the delay control output signal provided by the at least one fuse and provide a decoded value to the delay control circuit.
14. A method of applying a variable delay to a control signal of a sense amplifier within a programmable logic device, the method comprising:
programming a value into at least one configuration fuse within the programmable logic device, wherein the at least one configuration fuse comprises programmable static random access memory adapted to store and provide a value having logical high and logical low signal levels based on the programming;
configuring the programmable logic device for its intended operation during the programming, wherein the programming further programs the configuration memory of the programmable logic device; and
delaying the control signal by a selected amount of delay based on the value stored in the at least one configuration fuse.
15. The method of claim 14 , wherein the control signal determines when to enable the sense amplifier.
16. The method of claim 14 , further comprising decoding the value stored in the at least one configuration fuse.
17. The method of claim 14 , further comprising reprogramming the at least one configuration fuse to store a different value.