Control signal generation for a low jitter switched-capacitor frequency synthesizer
View Patent ↗A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.
1. A control signal generator for a switched-capacitor ripple-smoothing filter, comprising:
a phase detector configured to compare the phases of a reference signal and a feedback signal and generate a non-delayed up signal and a non-delayed down signal responsive to the phase comparison;
a programmable delay circuit configured to delay the non-delayed up and down signals to provide an up signal and a down signal;
a divider circuit configured to respond to the up and down signals to provide a divided clock signal; and
a non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals.
2. The control signal generator of claim 1 , further comprising:
a latch configured to assert a reset signal responsive to the assertion of either the hold even signal or the hold odd signal.
3. The control signal generator of claim 2 , wherein the latch is configured to assert the reset signal such that the reset signal and the up and down signals are non-overlapped.
4. The control signal generator of claim 2 , wherein the latch is further configured to de-assert the reset signal responsive to the assertion of either the non-delayed up signal or the non-delayed down signal.
5. The control signal generator of claim 1 , wherein the programmable delay circuit comprises a first programmable delay circuit configured to delay the non-delayed up signal and a second programmable delay circuit configured to delay the non-delayed down signal.
6. The control signal generator of claim 1 , wherein the non-delayed up signal, the non-delayed down signal, the up signal, and the down signal are all differential signals.
7. The control signal generator of claim 6 , wherein the non-delayed up signal, the non-delayed down signal, the up signal, and the down signal are all single-ended signals.
8. The control signal generator of claim 5 , wherein the first programmable delay circuit comprises a plurality of selectable inverters, wherein by varying the selection of the selectable inverters, the delay of the up signal with respect to the non-delayed up signal is varied.
9. The control signal generator of claim 8 , further comprising:
a non-volatile memory for storing control signals for the plurality of selectable inverters, wherein if a given selectable inverter's control signal is asserted, the given selectable inverter will contribute to the delay provided by the first programmable delay circuit.
10. The control signal generator of claim 5 , wherein the second programmable delay comprises a plurality of selectable inverters, wherein by varying the selection of the selectable inverters, the delay of the down signal with respect to the non-delayed down signal is varied.
11. The control signal generator of claim 10 , further comprising:
a non-volatile memory for storing control signals for the plurality of selectable inverters, wherein if a given selectable inverter's control signal is asserted, the given selectable inverter will contribute to the delay provided by the second programmable delay circuit.
12. A method of generating control signals for a switched-capacitor ripple-smoothing filter, comprising:
programmably delaying a periodically-pulsed non-delayed up signal and a periodically-pulsed non-delayed down signal to provide a periodically-pulsed up and down signal;
asserting a timing signal from the end of each up and down pulse cycle to the end of the subsequent up and down pulse cycle;
processing the timing signal to generate a non-overlapped hold even signal and a hold odd signal, and
processing the timing signal and the non-delayed up signal and the non-delayed down signals to provide a non-overlapped reset signal.
13. The method of claim 12 , further comprising:
simulating the operation of the switched-capacitor ripple-smoothing filter to determine the amount of programmable delay provided to the non-delayed up and down signals.
14. The method of claim 13 , further comprising: based upon the simulation results, adjusting the amount of programmable delay to optimize an operation speed provided by the switched-capacitor ripple-smoothing filter.
15. A control signal generator for a switched-capacitor ripple-smoothing filter, comprising:
a phase detector configured to compare the phases of a reference signal and a feedback signal and generate an up signal and a down signal responsive to the phase comparison;
a programmable delay circuit configured to delay the up and down signals;
a divider circuit configured to respond to the programmably delayed up and down signals to provide a divided clock signal; and
a clock generator configured to respond to the divided clock signal to provide hold even and hold odd signals.
16. The control signal generator of claim 15 , wherein the clock generator is a non-overlapped clock generator.