Programmable current output buffer
View Patent ↗A buffer for a programmable device has source current circuitry, sink current circuitry, one or more input nodes, one or more output nodes, and switch circuitry. The source current circuitry can be programmably controlled to generate a plurality of different total source currents, and the sink current circuitry can be programmably controlled to generate a plurality of different total sink currents. The one or more input nodes can receive one or more input signals, and the one or more output nodes can present one or more output signals. The switch circuitry can selectively apply at least one of a total source current and a total sink current to the one or more output nodes based on the one or more input signals.
1. A programmable device having a buffer, the buffer comprising:
source current circuitry comprising a plurality of current sources adapted to be programmably controlled to sequentially generate a plurality of different total source currents;
sink current circuitry comprising a plurality of current sinks adapted to be programmably controlled to sequentially generate a plurality of different total sink currents;
one or more input nodes adapted to receive one or more input signals;
one or more output nodes adapted to present one or more output signals; and
switch circuitry adapted to selectively apply at least one of a total source current and a total sink current to the one or more output nodes based on the one or more input signals.
2. The invention of claim 1 , wherein:
the buffer is a differential buffer;
the one or more input nodes comprise first and second input nodes adapted to receive first and second input signals;
the one or more output nodes comprise first and second output nodes adapted to present first and second output signals; and
the switch circuitry is adapted to selectively apply either (1) the total source current to the first output node and the total sink current to the second output node or (2) the total source current to the second output node and the total sink current to the first output node.
3. The invention of claim 1 , further comprising an operational amplifier adapted to contribute current to either the total source current or the total sink current.
4. The invention of claim 3 , wherein the operational amplifier is adapted to (1) receive a reference voltage signal and a sampled voltage signal corresponding to a common-mode voltage for the buffer and (2) generate an opamp output signal that drives the sampled voltage signal towards the reference voltage signal.
5. The invention of claim 1 , wherein:
the source current circuitry comprises:
N current source devices connected in parallel at their channel nodes; and
N−1 switches, each switch connected between the gates of a different pair of adjacent current source devices; and
the sink current circuitry comprises:
M current sink devices connected in parallel at their channel nodes; and
M−1 switches, each switch connected between the gates of a different pair of adjacent current sink devices.
6. The invention of claim 5 , wherein:
the N current source devices comprises an unswitched, first current source device and N−1 switched current source devices; and
the M current sink devices comprises an unswitched, first current sink device and N−1 switched current sink devices.
7. The invention of claim 6 , wherein:
the first current source device generates a first source current having a magnitude different from a first sink current generated by the first current sink device; and
each switched current source device generates a switched source current having a magnitude substantially equal to a switched sink current generated by a corresponding switched current sink device.
8. The invention of claim 7 , further comprising an operational amplifier adapted to contribute a current having a magnitude substantially equal to a difference between the magnitude of the first source current and the magnitude of the first sink current.
9. The invention of claim 5 , wherein:
the N−1 switches are independently programmable; and
the M−1 switches are independently programmable.
10. The invention of claim 1 , wherein:
the source current circuitry comprises N switched current sources connected in parallel; and
the sink current circuitry comprises M switched current sinks connected in parallel.
11. The invention of claim 10 , wherein:
each switched current source comprises a switch and a current source device connected in series; and
each switched current sink comprises a switch and a current sink device connected in series.
12. The invention of claim 10 , wherein:
the N switched current sources are independently programmable; and
the M switched current sources are independently programmable.
13. The invention of claim 1 , further comprising an output load adapted to convert each output signal from a current signal into a voltage signal.
14. The invention of claim 13 , wherein the voltage signals corresponding to the different total current sources and different total current sinks correspond to a plurality of different signaling applications.
15. The invention of claim 14 , wherein:
the plurality of different signaling applications comprise LVDS, RSDS, and Hyper Transport; and
the programmable device is implemented as a single integrated circuit.
16. A method for processing an input signal to present an output signal at one or more output nodes, the method comprising:
programmably generating a total source current from among a plurality of different supported total source currents using source current circuitry comprising a plurality of current sources adapted to be programmably controlled to sequentially generate the plurality of different supported total source currents;
programmably generating a total sink current from among a plurality of different supported total sink currents using sink current circuitry comprising a plurality of current sinks adapted to be programmably controlled to sequentially generate the plurality of different supported total sink currents; and
selectively applying at least one of the total source current and the total sink current to the one or more output nodes based on the one or more input signals.
17. The invention of claim 16 , wherein:
the output signal is presented at two output nodes; and
the total source current and the total sink current are selectively applied to the two output nodes based on the input signal.
18. An apparatus for processing an input signal to present an output signal at one or more output nodes, the apparatus comprising:
means for programmably generating a total source current from among a plurality of different supported total source currents, said means comprising a plurality of current sources adapted to be programmably controlled to sequentially generate the plurality of different supported total source currents;
means for programmably generating a total sink current from among a plurality of different supported total sink currents, said means comprising a plurality of current sinks adapted to be programmably controlled to sequentially generate the plurality of different supported total sink currents; and
means for selectively applying at least one of the total source current and the total sink current to the one or more output nodes based on the one or more input signals.
19. The invention of claim 18 , wherein:
the output signal is presented at two output nodes; and
the total source current and the total sink current are selectively applied to the two output nodes based on the input signal.