Memory output data systems and methods with feedback
View Patent ↗Systems and methods provide output data from a memory. For example, in accordance with an embodiment of the present invention, techniques are disclosed for providing glitch-free output data from a memory through feedback of the output data signal.
1. An integrated circuit comprising:
a memory;
a memory array, within the memory, having a plurality of memory cells;
output latches, within the memory, adapted to receive data from the memory array; and
an output multiplexer, within the memory, adapted to receive the data from the output latches and provide an output data signal from the memory, wherein the output latches are further adapted to receive the output data signal from the output multiplexer to selectively provide to the output multiplexer.
2. The integrated circuit of claim 1 , wherein the output latches are controlled by a latch control signal, which determines whether the output latches provide the data received from the memory array or feedback data received from the output data signal.
3. The integrated circuit of claim 1 , further comprising:
bitline column multiplexers, coupled between the output latches and the memory array, adapted to receive the data from the memory array; and
sense amplifiers, coupled between the bitline column multiplexers and the output latches, adapted to receive the data from the bitline column multiplexer and provide the data to the output latches.
4. The integrated circuit of claim 1 , wherein the output multiplexer is controlled by a multiplexer control signal that controls a selection of the data from the output latches to provide as the output data signal.
5. The integrated circuit of claim 1 , wherein a feedback control signal determines whether the output latches provide the data from the memory array or the data from the output data signal to the output multiplexer, the output multiplexer controlled by a multiplexer control signal that controls a selection of the data from the output latches to provide as the output data signal.
6. The integrated circuit of claim 5 , further comprising a delay element adapted to delay the multiplexer control signal sufficiently to allow the data from the output data signal to be provided to the output multiplexer from the output latches.
7. The integrated circuit of claim 5 , further comprising a matched path adapted to delay the multiplexer control signal and substantially match a time delay associated with the output latches for providing the data from the output data signal to the output multiplexer.
8. The integrated circuit of claim 5 , further comprising:
a matched path adapted to receive the feedback control signal and substantially match a time delay associated with the output latches for providing the data from the output data signal to the output multiplexer; and
a latch, coupled to the matched path, for receiving the feedback control signal from the matched path and the multiplexer control signal and, based on a timing of the feedback control signal, providing the multiplexer control signal to the output multiplexer.
9. The integrated circuit of claim 8 , wherein the multiplexer control signal arrives at the output multiplexer prior to the arrival of the data read from the memory array on a subsequent read cycle.
10. An integrated circuit comprising:
a memory;
a read circuit, within the memory, adapted to read data stored in the memory; and
an output multiplexer, within the memory, adapted to receive the data from the read circuit, wherein the output multiplexer provides an output data signal from the memory and further provides the output data signal back to the read circuit.
11. The integrated circuit of claim 10 , wherein the read circuit is adapted to receive a feedback control signal, which determines whether the read circuit provides the data read from the memory or the data provided by the output data signal, and the output multiplexer is adapted to receive a control signal for selecting the data from the read circuit.
12. The integrated circuit of claim 11 , wherein a timing of the control signal is maintained so that the data from the output data signal is provided to the output multiplexer from the read circuit before the control signal reaches the output multiplexer.
13. The integrated circuit of claim 11 , further comprising a delay element adapted to delay the control signal until the data from the output data signal is provided to the output multiplexer from the read circuit.
14. The integrated circuit of claim 11 , further comprising a latch adapted to delay the control signal until the data from the output data signal is provided to the output multiplexer from the read circuit.
15. The integrated circuit of claim 11 , wherein the memory is configurable.
16. A method of providing data from a memory, the method comprising;
reading data stored in the memory;
latching the data within the memory;
selecting from the latched data to provide an output data signal from the memory; and
feeding back, within the memory, the latched data provided on the output data signal for the latching.
17. The method of claim 16 , wherein the latched data fed back on the output data signal is provided on the output data signal prior to a subsequent read of the memory.
18. The method of claim 16 , wherein the memory is configurable.
19. The method of claim 16 , wherein the output data signal is glitch free.
20. The method of claim 16 , further comprising delaying the selecting to allow the latched data to be fed back.