SERDES with programmable I/O architecture

1. A programmable interconnect circuit, comprising:

a plurality of SERDES circuits dedicated to communicating high-speed data;

a plurality of input/output (I/O) circuits dedicated to communicating low-speed data; and

a routing structure configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays.

2. The programmable interconnect circuit of claim 1 , wherein the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.

3. The programmable interconnect circuit of claim 2 , wherein the I/O circuits are organized into a plurality of I/O blocks, each I/O block including a subset of the I/O circuits, and wherein the low-speed routing structure comprises a plurality of low-speed routing structures, each low-speed routing structure corresponding to an I/O block.

4. The programmable interconnect circuit of claim 3 , wherein each low-speed routing structure comprises a data-path routing structure and a control-path routing structure, the data-path routing structure being configured to provide signals to the output registers in the corresponding I/O block, the control-path routing structure being configured to provide signals to the corresponding I/O block's control array.

5. The programmable interconnect circuit of claim 4 , wherein each data-path routing structure comprises a first level data-path routing structure having a partially-populated switch matrix and a second level data-path routing structure, the first level data-path routing structure being configured to receive signals from the plurality of I/O blocks and a plurality of SERDES circuits and to route the received signals into a first plurality of signals, the second level data-path routing structure being configured to receive the first plurality of signals and route them to the corresponding I/O block's output registers.

6. The programmable interconnect circuit of claim 5 , wherein each second level data-path routing structure comprises a fully populated switch matrix.

7. The programmable interconnect circuit of claim 1 , wherein the routing structure is configurable to provide the couplings simultaneously or alternatively.

8. The programmable interconnect circuit of claim 1 , wherein each SERDES circuit is configurable for communicating high-speed data using at least one of LVDS, CML, and LVPECL signaling protocols.

9. The programmable interconnect circuit of claim 1 , wherein the interconnect circuit is embodied in a programmable logic device with dedicated low-speed I/O pins associated with the I/O circuits and dedicated high-speed pins associated with the SERDES circuits.

10. The programmable interconnect circuit of claim 1 , wherein each I/O circuit includes an output register configured to register a signal from the routing structure and to provide the registered signal to a dedicated low-speed I/O pin and an input register configured to register a signal from the dedicated low-speed I/O pin and provide the registered signal to the routing structure, and wherein each SERDES circuit is associated with a dedicated high-speed I/O pin.

11. The programmable interconnect circuit of claim 1 , wherein each I/O circuit is configurable for communicating low-speed data using at least one of LVCMOS, LVTTL, and SSTL signaling protocols.

12. The programmable interconnect circuit of claim 1 , wherein the I/O circuits are organized into a plurality of I/O blocks, each I/O block including a control array configured to receive signals from the routing structure and to form product term control signals from the received signals for the control of the I/O block.

13. A programmable interconnect circuit, comprising:

a plurality of SERDES circuits;

a plurality of input/output (I/O) blocks, each I/O block including a plurality of I/O circuits; and

a routing structure configurable to receive input signals from the plurality of I/O blocks and the plurality of SERDES circuits and for programmably routing with deterministic delays the received input signals to selected I/O blocks and to selected SERDES circuits.

14. The programmable interconnect circuit of claim 13 , wherein each SERDES circuit is configurable for at least one of LVDS, CML, and LVPECL signaling.

15. The programmable interconnect circuit of claim 13 , wherein each I/O circuit is configurable for at least one of LVCMOS, LVTTL, and SSTL signaling.

16. A method of programmably routing signals through a programmable interconnect device, comprising:

providing in the device a plurality of SERDES circuits dedicated to communicating high-speed data, a plurality of input/output (I/O) circuits dedicated to communicating low-speed data, and a routing structure configurable to couple any of the I/O circuits or SERDES circuits to any of the other I/O circuits or SERDES circuits over routing paths having deterministic routing delays;

to route a low-speed data signal through the device, configuring the routing structure to couple an I/O circuit to another I/O circuit;

to route a high-speed data signal through the device, configuring the routing structure to couple a SERDES circuit to another SERDES circuit;

to convert a low-speed input data signal to a high-speed output data signal, configuring the routing structure to couple an I/O circuit to a SERDES circuit; and

to convert a high-speed input data signal to a low-speed output data signal, configuring the routing structure to couple a SERDES circuit to an I/O circuit.

17. The method of claim 16 , wherein each SERDES circuit associates with a dedicated high-speed pin and each I/O circuit associates with a dedicated low-speed pin, the method further comprising:

routing a low-speed data signal through the device from a low-speed pin to another low-speed pin; and

routing a high-speed data signal through the device from a high-speed pin to another high-speed pin.

18. The method of claim 16 , further comprising simultaneously routing both high-speed and low-speed data through the device.

19. The method of claim 16 , further comprising simultaneously converting high-speed input data signals to low-speed output data signals and low-speed input data signals to high-speed output data signals through the device.

20. The method of claim 16 , wherein the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.