Testing embedded memory in an integrated circuit
View Patent ↗An integrated circuit includes a first bus and at least one array of embedded memories. Each array includes a second bus such as a bidirectional bus coupled to the embedded memories and to the first bus such that test vectors in the form of data words can be written from the first bus to selected embedded memories in the array. Also included is a built-in-self-test (BIST) circuit operable to compare data words on the first bus to data words read back from the selected embedded memories through the bidirectional bus.
1. An integrated circuit, comprising:
a first bus;
at least one array of embedded memories;
a bidirectional data bus coupled to the array of embedded memories and to the first bus such that test vectors may be written from the first bus to selected embedded memories in the array through the bidirectional data bus;
a test circuit adapted to compare test vectors on the first bus to test vectors read back from the selected embedded memories in the array through the bidirectional data bus to provide a comparison result; and
a tri-state buffer coupled between the first bus and the bidirectional bus, the tri-state buffer adapted to being driven into a high-impedance mode while test vectors are read back from the embedded memories.
2. The integrated circuit of claim 1 , wherein the first bus is a directional bus.
3. The integrated circuit of claim 1 including a plurality of arrays of embedded memories, wherein each array includes a separate test circuit.
4. The integrated circuit of claim 3 , wherein each array includes a built-in-self-test (BIST) circuit and each BIST circuit includes a scan register adapted for forming a scan chain with the scan registers of the other BIST circuits such that bits representing comparison results can be shifted through the scan chain.
5. The integrated circuit of claim 1 , wherein the test circuit includes a built-in-self-test (BIST) circuit.
6. The integrated circuit of claim 1 , wherein the tri-state buffer is adapted to respond to a write enable signal.
7. The integrated circuit of claim 1 , wherein the tri-state buffer is adapted to respond to an initialization signal.
8. The integrated circuit of claim 1 , wherein the test circuit includes an XOR gate adapted for comparing test vectors from the first bus to the test vectors read back from the selected embedded memories in the array.
9. The integrated circuit of claim 8 , wherein the XOR gate comprises a plurality of XOR gates.
10. The integrated circuit of claim 9 , wherein the test circuit further includes a wired NOR circuit to collapse outputs from the plurality of XOR gates into a single comparison result bit.
11. An integrated circuit, comprising:
a first bus;
at least one array of embedded memories;
a bidirectional data bus coupled to the array of embedded memories and to the first bus such that test vectors may be written from the first bus to selected embedded memories in the array through the bidirectional data bus;
a test circuit configured to compare test vectors on the first bus to test vectors read back from the selected embedded memories in the array through the bidirectional data bus to provide a comparison result; and
a tri-state buffer coupled between the first bus and the bidirectional bus, the tri-state buffer adapted to being driven into a high-impedance mode while test vectors are read from the embedded memories,
wherein the first bus is adapted for carrying local address signals such that test vectors written from the first bus to the embedded memories are written to the locations specified by the local address signals, the embedded memories being operable to respond to a global address signal identifying a particular embedded memory such that only the embedded memory identified by the global address signal is written to at the address specified by the local address signal.
12. The integrated circuit of claim 11 , wherein the first bus is a directional bus.
13. The integrated circuit of claim 11 including a plurality of arrays of embedded memories and associated test circuits, wherein each test circuit includes a built-in-self-test (BIST) circuit and each BIST circuit includes a scan register adapted for forming a scan chain with the scan registers of the other BIST circuits such that bits representing comparison results can be shifted through the scan chain.
14. The integrated circuit of claim 11 , wherein the tri-state buffer is adapted for responding to at least one of a write enable signal and an initialization signal.