Programmable logic device with enhanced wide and deep logic capability
View Patent ↗A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may form product terms of a fixed input width. The cluster is configured to provide input width cascading between the blocks. In addition, the cluster is configured to provide depth cascading such that sum of all the product terms from one logic block may be cascaded to another.
1. A programmable logic device, comprising:
a routing structure configured to provide logical inputs;
a plurality of logic blocks, each logic block including:
a programmable AND array to provide a plurality of product terms from a plurality of the logical inputs provided by the routing structure, the plurality of product terms being arranged the same for each logic block; and
an AND gate for each product term, each AND gate being operable to selectively receive its product term and/or the corresponding product terms in the remaining logic blocks, each AND gate thereby forming a cascaded product term based on the selected product terms, whereby for each product term received by the AND gate, the input width for the cascaded product term is incremented by the plurality of logical inputs.
2. The programmable logic device of claim 1 , wherein each AND gate is operable to selectively receive its product term and/or the corresponding product terms in the remaining logic blocks through the operation of programmable fuses.
3. The programmable logic device of claim 1 , wherein each logic block further comprises a plurality of macrocells, each macrocell coupling to a cluster OR gate operable to sum a cluster of the cascaded product terms from the AND gates such that each macrocell may register the sum of cascaded product terms from its cluster OR gate.
4. The programmable logic device of claim 1 , wherein each logic block further comprises a plurality of macrocells, each macrocell coupling to an N-input cluster OR gate operable to sum a plurality of N of the cascaded product terms from the AND gates such that each macrocell may register the sum of cascaded product terms from its N-input cluster OR gate, the macrocells being arranged from a first macrocell to a last macrocell such that the first macrocell's N-input cluster OR gate may sum the first through the Nth cascaded product term, and so on.
5. The programmable logic device of claim 1 , wherein each logic block further comprises a plurality of multiplexers corresponding on a one-to-one basis with the plurality of AND gates, wherein each multiplexer is operable to select between its AND gate's product term input and the cascaded product term output to provide a selected signal, and wherein each logic block includes a plurality of macrocells, each macrocell coupling to a cluster OR gate operable to sum a cluster of the selected signals such that each macrocell may register a sum of cascaded product terms or a sum of product terms, whereby the inter-logic-block width cascading provided by the plurality of AND gates may be bypassed.
6. The programmable logic device of claim 1 , wherein each logic block further comprises:
a plurality of macrocells, each macrocell coupling to a cluster OR gate operable to sum a cluster of the cascaded product terms from the AND gates such that each macrocell may register the sum of cascaded product terms from its cluster OR gate; and
intra-block product term depth cascading circuitry configured to add the sums of cascaded product terms corresponding to the plurality of macrocells to form a depth cascaded sum of product terms, each macrocell being coupled to the intra-block product term depth cascading circuitry such that each macrocell may also register the depth cascaded sum of product terms.
7. The programmable logic device of claim 6 , further comprising depth logic circuitry configured to provide inter-block depth cascading configured such that the depth cascaded sum of product terms from one macrocell in one logic block in the plurality of logic blocks may be directly cascaded through the depth logic circuitry to the corresponding macrocell in another logic block in the plurality.
8. The programmable logic device of claim 6 , wherein each logic block further comprises a cascading OR gate for each macrocell, wherein each cascading OR gate is configured to receive its macrocell's depth cascaded sum of product terms and to receive the depth cascaded sum of product terms from the corresponding macrocell in at least one other logic block.
9. The programmable logic device of claim 6 , wherein each logic block further comprises a 2-input cascading OR gate for each macrocell, wherein each 2-input cascading OR gate is configured to receive its macrocell's depth cascaded sum of product terms and to receive the depth cascaded sum of product terms from the corresponding macrocell in one other logic block.
10. The programmable logic device of claim 6 , wherein each logic block further comprises a 3-input cascading OR gate for each macrocell, wherein each 3-input cascading OR gate is configured to receive its macrocell's depth cascaded sum of product terms and to receive the depth cascaded sum of product terms from the corresponding macrocell in two other logic blocks.
11. The programmable logic device of claim 6 , wherein each logic block further comprises a 4-input cascading OR gate for each macrocell, wherein each 410 input cascading OR gate is configured to receive its macrocell's depth cascaded sum of product terms and to receive the depth cascaded sum of product terms from the corresponding macrocell in three other logic blocks.
12. The programmable logic device of claim 1 , wherein each logic block further comprises a plurality of macrocells, each macrocell coupling to a cluster OR gate operable to sum a cluster of the cascaded product terms from the AND gates such that each macrocell may register the sum of cascaded product terms from its cluster OR gate; and wherein the programmable logic device further comprises inter-block depth cascading circuitry having a cascading OR gate for each macrocell and a product term sharing array, wherein each cascading OR gate is configured to sum the cascaded product terms summed by its macrocell's cluster OR gate and the output of another cascading OR gate and to provide a cascaded sum to the product term sharing array; wherein the product term sharing array is configured to, for each macrocell, add the cascaded sum with cascaded sums from other cascading OR gates to provide an inter-block depth cascaded sum of products output to the macrocell.
13. The programmable logic device of claim 12 , wherein the product term sharing array comprises a partially populated switch matrix.
14. A method using a plurality of logic blocks, wherein each logic block has a programmable AND array configured to produce a plurality of product terms using a plurality of X logical inputs, and wherein each logic block includes a plurality of macrocells, each macrocell being configured to sum a subset of the plurality of product terms, the method comprising:
cascading the sum of the subset of product terms from each macrocell at a first one of the logic blocks to form a first sum of product terms;
cascading the sum of the subset of product terms from each macrocell at a second one of the logic blocks to form a second sum of product terms; and
summing the first and second sum of product terms to form an inter-block cascaded sum of product terms.
15. The method of claim 14 , further comprising:
coupling the subset of product terms from a first macrocell in the first logic block to a second macrocell in the second logic block; and
forming an inter-block width cascaded subset of product terms using the subset of product terms from each of the first and second macrocells, whereby the inter-block width is cascaded in an increment of X logical inputs.
16. A programmable logic device, comprising:
a plurality of logic blocks, wherein each logic block includes a programmable AND array for forming product terms using a plurality of X logical inputs, and wherein each logic block includes a plurality of macrocells, each macrocell including an OR gate for summing a subset of product terms received from the programmable AND array; and
means for input-width cascading between the logic blocks such that the input width of the product terms summed by each OR gate may be increased by increments of X logical inputs by directly coupling product terms through the means.
17. The programmable logic device of claim 16 , wherein the means for input-width cascading is configured to provide bi-directional cascading between the logic blocks.
18. A programmable logic device, comprising:
a plurality of logic blocks, wherein each logic block includes a programmable AND array for forming product terms using a plurality of X logical inputs, and wherein each logic block includes a plurality of macrocells, each macrocell including an OR gate for summing a subset of product terms received from the programmable AND array; and
means for depth cascading between the logic blocks such that the sum of the subset of product terms from each macrocell may be incremented by the subset of product term increments by directly coupling the sums of the subsets of product terms through the means for depth cascading.
19. The programmable logic device of claim 17 , wherein the means for depth cascading is configured to provide bi-directional cascading between the logic blocks.
20. The programmable logic device of claim 17 , wherein the means for depth cascading is configured to provide unidirectional cascading between the logic blocks.