Reducing bit line leakage current in non-volatile memories
View Patent ↗In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.
1. A method for reducing bit line leakage current, the method comprising:
biasing an unselected program word line to a bias voltage, the unselected program word line being connected to a memory cell, the memory cell including a breakdown transistor connected in series to a select transistor, the select transistor being connected to a read word line and configured to select or unselect the memory cell, the breakdown transistor being connected to the unselected program word line and configured to form a conductive path based on an application of a programming pulse.
2. The method of claim 1 , wherein the unselected program word line is biased during a read operation.
3. The method of claim 1 , wherein the unselected program word line is biased during a discharge period of a selected bit line.
4. The method of claim 3 , further comprising floating the unselected program word line after the discharge period.
5. The method of claim 1 , wherein the bias voltage is less than a reference voltage.
6. The method of claim 1 , wherein the bias voltage is about equal to a reference voltage.
7. A method for reducing bit line leakage current, the method comprising:
biasing an unselected memory cell to a negative bias voltage during a read operation, the unselected memory cell including a breakdown transistor connected in series to a select transistor, the select transistor being connected to a read word line and configured to select or unselect the memory cell, the breakdown transistor being connected to a program word line and configured to form a conductive path based on an application of a programming pulse by way of the program word line.
8. A memory, comprising:
a memory cell including a breakdown transistor connected in series to a select transistor, the select transistor being connected to a read word line and configured to select or unselect the memory cell, the breakdown transistor being connected to a program word line and configured to form a conducting path based on an application of a programming pulse by way of the program word line; and
a word line decoder connected to the memory cell by the program word line, the word line decoder being configured to bias the program word line to a bias voltage when the program word line is unselected.
9. The memory of claim 8 , wherein the word line decoder is configured to bias the program word line during a read operation.
10. The memory of claim 8 , wherein the memory further comprises a column decoder connected to the memory cell by a bit line.
11. The memory of claim 10 , wherein the word line decoder is configured to bias the program word line during a discharge period of the bit line when the bit line is selected.
12. The memory of claim 8 , wherein the program word line is biased to the bias voltage during one or more of a read operation or a program operation.
13. The memory of claim 8 , wherein the word line decoder is further connected to the memory cell by a read word line and a write word line.
14. The memory of claim 8 , wherein the bias voltage is less than a reference voltage.
15. The memory of claim 8 , wherein the bias voltage is about equal to a reference voltage.
16. A memory, comprising:
a memory cell including a breakdown transistor connected in series to a select transistor, the select transistor being connected to a read word line and configured to select or unselect the memory cell, the breakdown transistor being connected to a program word line and configured to form a conducting path based on an application of a programming pulse by way of the program word line;
a voltage source connected to the memory cell, the voltage source being configured to bias the memory cell to a negative bias voltage; and
a switch connected to the memory cell and the voltage source, the switch being configured to connect the voltage source to the memory cell during a read operation and when the memory cell is unselected.
17. A non-volatile memory, comprising:
a memory cell including a breakdown transistor connected in series to a select transistor, the select transistor being connected to a read word line and configured to select or unselect the memory cell, the breakdown transistor being connected to a program word line and configured to form a conducting path based on an application of a programming pulse by way of the program word line; and
a voltage source connected to the memory cell by the program word line, the voltage source being configured to bias the program word line to a bias voltage when the program word line is unselected.
18. The non-volatile memory of claim 17 , further comprising a switch connected to the memory cell and the voltage source by the program word line, the switch being configured to connect the memory cell to the voltage source during a read operation.
19. The non-volatile memory of claim 17 , further comprising a switch connected to the memory cell and the voltage source by the program word line, the switch being configured to connect the memory cell to the voltage source during a discharge period of a selected bit line.
20. The non-volatile memory of claim 17 , wherein the bias voltage is about 100 mV.