Write enhancement for one time programmable (OTP) semiconductors
A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line. The voltage across an oxide layer between the gate electrode and channel region of the programming element ruptures the oxide layer and effectively programs the programming element.
1. In a memory cell having a programmable element and a pass transistor connectable in series to a bit line, a method of programming the memory cell comprising applying a first programming pulse by:
setting a first voltage of a first polarity on a first gate electrode of the programming element;
setting a second voltage of the first polarity on a second gate electrode of the pass transistor;
setting a third voltage on a bit line connected to the pass transistor, the third voltage of a second polarity opposite the first polarity;
rupturing an oxide layer between the first gate electrode and a channel region of the programming element; and
applying a second programming pulse including a negative voltage.
2. The method of claim 1 wherein the first polarity is positive.
3. The method of claim 2 wherein the third voltage is −1.0 to −2.0 volts.
4. The method of claim 3 wherein the first voltage is +5.0 to +6.0 volts.
5. The method of claim 4 wherein the second voltage is +1.5 to +2.5 volts.
6. The method of claim 1 wherein the pass transistor comprises the second gate electrode over a channel region between two N-type source/drain regions.
7. The method of claim 1 wherein the programming element comprises a first gate electrode over a channel region contiguous to at least one of the two N-type source/drain regions.
8. The method of claim 1 further comprising:
allowing a channel region below the first gate electrode of the programming element to electrically float.
9. The method of claim 8 further comprising:
allowing a channel region below the gate electrode of the pass transistor to electrically float.
10. In an array of one-time programmable (OTP) memory cells, each memory cell having a MOSFET pass transistor with a gate electrode over a channel region between two source/drain regions, and a MOSFET programming element with a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor, the other source/drain region of the MOSFET pass transistor coupled to a bit line, a method of programming the memory cell comprising applying a first programming pulse by:
setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor;
setting a second voltage of the first polarity on the gate electrode of the programming element;
setting a third voltage of a second polarity on the bit line;
whereby a voltage across an oxide layer between the gate electrode and channel region of the programming element is created to rupture the oxide layer and program the programming element; and
applying a second programming pulse including a negative voltage.
11. The method of claim 10 wherein the first polarity is positive with respect to ground and the third polarity is negative with respect to ground.
12. The method of claim 11 wherein the third voltage is in a range between −0.5 to −1.0 volts.
13. The method of claim 12 wherein the first voltage is approximately +5.5 volts.
14. The method of claim 13 wherein the second voltage is approximately +2.0 volts.
15. The method of claim 10 further comprising:
allowing a channel region below the gate electrode of the programming element to electrically float.
16. The method of claim 10 further comprising:
allowing a channel region below the gate electrode of the pass transistor to electrically float.
17. A semiconductor device comprising:
an array of one-time programmable (OTP) memory cells, each memory cell having
a MOSFET pass transistor having two source/drain regions, and a gate electrode over a channel region between the two source/drain regions;
a MOSFET programming element having two source/drain regions and a gate electrode over a channel region between the two source/drain regions, one of the source/drain regions either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor;
a first word line connected to the gate of the MOSFET pass transistor;
a second word line connected to the gate electrode of the MOSFET programming element;
a bit line connected to the source/drain region of the MOSFET pass transistor not part of, nor connected to, a source/drain region of the MOSFET programming element; and
a negative voltage source coupled to the bit line during a first programming pulse during programming of the memory cell, and again coupled to the bit line during a second programming pulse.
18. The semiconductor device of claim 17 wherein the channel regions of the MOSFET programming element transistors are electrically floating.
19. The semiconductor device of claim 18 wherein the channel regions of the MOSFET pass transistors are electrically floating.