Interface block architectures
View Patent ↗In accordance with an embodiment of the present invention, a programmable logic device includes a memory adapted to store information in the programmable logic device, an input/output circuit adapted to transfer information into or out of the programmable logic device, and an interconnect architecture adapted to route information within the programmable logic device. An interface circuit is provided to couple the memory and the input/output circuit to the interconnect architecture.
1. A programmable logic device comprising:
a memory adapted to store information in the programmable logic device;
an input/output circuit adapted to transfer information into or out of the programmable logic device;
an interconnect architecture adapted to route information within the programmable logic device; and
an interface circuit adapted to couple the memory and the input/output circuit to the interconnect architecture, wherein the interface circuit comprises a routing switch matrix and an input/output switch matrix.
2. The programmable logic device of claim 1 , further comprising a plurality of logic blocks coupled to the interconnect architecture and forming a logic block array, wherein the memory is disposed outside of the logic block array.
3. The programmable logic device of claim 1 , wherein the interface circuit is further adapted to transfer information between the interconnect architecture and the memory and the input/output circuit.
4. The programmable logic device of claim 1 , further comprising at least a second input/output circuit, wherein the interface circuit is further adapted to couple the at least second input/output circuit to the interconnect architecture.
5. The programmable logic device of claim 1 , wherein the interconnect architecture comprises vertical and horizontal routing resources, and wherein the interface circuit couples the memory to the vertical routing resource and the horizontal routing resource and couples the input/output circuit to only the vertical routing resource or the horizontal routing resource.
6. The programmable logic device of claim 1 , wherein the programmable logic device comprises at least one of a field programmable gate array and a complex programmable logic device.
7. The programmable logic device of claim 1 , further comprising a plurality of the input/output circuits, wherein the interface circuit comprises a plurality of common interface circuits, with each of the common interface circuits providing interface routing of signals for the memory and at least one of the input/output circuits.
8. A programmable logic device comprising:
a memory block adapted to store information;
a plurality of input/output circuits adapted to transmit or receive information for the programmable logic device;
means for routing information within the programmable logic device, wherein the routing means comprises vertical and horizontal routing resources; and
means for interfacing a portion of the memory block and a number of the input/output circuits to the routing means, wherein the interfacing means couples the portion of the memory block to the vertical routing resource and the horizontal routing resource and couples the number of the input/output circuits to only the vertical routing resource or the horizontal routing resource.
9. The programmable logic device of claim 8 , wherein the number of the input/output circuits equals four or more which are supported by the interfacing means.
10. The programmable logic device of claim 8 , further comprising a second memory block, wherein a corresponding one of the interfacing means couples a portion of the second memory block and at least another number of the input/output circuits to the routing means.
11. The programmable logic device of claim 8 , further comprising a plurality of logic blocks coupled to the routing means and forming a logic block array, wherein the memory block is disposed outside of the logic block array.
12. The programmable logic device of claim 8 , further comprising a plurality of logic blocks coupled to the routing means and forming a logic block array, wherein the memory block is disposed outside of the logic block array, wherein the number of the input/output circuits equals four or more which are supported by the interfacing means, and wherein the interfacing means couples the input/output circuits to only the vertical routing resource or the horizontal routing resource if disposed within a column or a row, respectively, of the logic block array.
13. The programmable logic device of claim 8 , wherein the programmable logic device comprises at least one of a field programmable gate array and a complex programmable logic device.
14. A method of providing an interface within a programmable logic device, the method comprising:
providing a memory block within the programmable logic device;
providing a first number of input/output circuits within the programmable logic device;
providing an interconnect circuit within the programmable logic device, wherein the interconnect structure comprises vertical and horizontal routing resources; and
interfacing the first number of input/output circuits and a portion of the memory block in combination to the interconnect circuit, wherein the interfacing couples the portion of the memory block to the vertical routing resource and the horizontal routing resource and couples the first number of input/output circuits to only the vertical routing resource.
15. The method of claim 14 , further comprising providing a plurality of logic blocks coupled to the interconnect architecture and forming a logic block array, wherein the memory block is disposed outside of the logic block array.
16. The method of claim 14 , further comprising providing a second number of input/output circuits within the programmable logic device, wherein the interfacing further interfaces the second number of input/output circuits and a second portion of the memory block to the interconnect architecture.
17. The method of claim 14 , wherein the first number of the input/output circuits equals four or more which are supported by the interfacing.
18. The method of claim 14 , wherein the programmable logic device comprises at least one of a field programmable gate array and a complex programmable logic device.
19. The method of claim 14 , further comprising providing a second number of input/output circuits within the programmable logic device, and wherein the interfacing couples the portion of the memory block to the vertical routing resource and the horizontal routing resource and couples the second number of input/output circuits to only the horizontal routing resource.
20. The method of claim 14 , further comprising providing a plurality of logic blocks coupled to the interconnect architecture and forming a logic block array, wherein the memory block is disposed outside of the logic block array, and wherein the interfacing couples the first number of input/output circuits to only the vertical routing resource or the horizontal routing resource if disposed within a column or a row, respectively, of the logic block array.